Direct Observation of the Impurity Gettering Layers in Polysilicon-Based Passivating Contacts for Silicon Solar Cells

Abstract

The formation of certain types of doped polysilicon passivating contacts for silicon solar cells is recently reported to generate very strong impurity gettering effects, revealing an important additional benefit of this passivating contact structure. This work investigates the underlying gettering mechanisms by directly monitoring the impurity redistribution during the contact formation and subsequent processes, via a combination of secondary ion mass spectrometry (SIMS), transmission electron microscopy (TEM), and minority carrier lifetime techniques. Microscopic features of the phosphorus and boron diffusion-doped polysilicon passivating contacts are also presented. Iron is used as a marker impurity in silicon to enable direct quantification of its concentration change in the bulk of the silicon wafers and in the surface layers that compose the contact structure. The results conclusively show that, for phosphorus-doped polysilicon passivating contacts, impurities are relocated from the silicon wafer bulk to the heavily phosphorus-doped polysilicon layer; while for the boron diffusion-doped polysilicon, the boron-rich layer (a silicon−boron compound) accounts for the majority of the gettering action.

Role of polysilicon in poly-Si/SiOxpassivating contacts for high-efficiency silicon solar cells

“…However, further increase in doping concentration caused the drop in bulk iV OC from 710 to 670 mV. This might be caused by the reappearance of gettered impurities, which is also represented by Liu et al 11 Thus, we concluded that poly-Si is required for contact because SiO x would get destroyed without poly-Si. The poly-Si layer plays the following roles: (1) contact, (2) in-diffusion barrier, and provides (3) eld effect and (4) gettering.…”

“…The gettering effect of the poly-Si passivating contact was studied by A. Liu. 10,11 In our research, the gettering effect was conrmed by etching poly-Si/SiO x and the in-diffused region, and repassivating the sample using a 10 nm-thick aluminum oxide layer. We conrmed that by increasing the doping concentration from 8 Â 10 19 cm À3 to 1.8 Â 10 20 cm À3 , the bulk quality improved as iV OC aer etching the poly-Si/c-Si, from 693 to 705 mV.…”

“…[3][4][5] To reduce the recombination loss, passivating contacts (also referred to as carrier-selective contacts) have been introduced for high-quality passivation with low contact resistance. 2,[5][6][7][8][9][10][11][12][13][14] The passivating contact cells differ from conventional cells in the following ways: (1) the recombination occurring at the metal-semiconductor junction is reduced by a passivation layer between the crystalline silicon and metal contact, and (2) the majority carriers can move to the metal contact, while the minority carriers cannot be moved from crystalline silicon to the metal contact owing to carrier selectivity.…”

Impurity Gettering by Boron‐ and Phosphorus‐Doped Polysilicon Passivating Contacts for High‐Efficiency Multicrystalline Silicon Solar Cells

“…The driving force of the impurity gettering by B‐doped layers is often a combination of segregation due to precipitation at the surface of the p+ layer, Fermi level effect, and Fe–B pairing . However, for heavily doped layers, the impurity gettering seems to be preferentially realized by the BRL . Segregation due to chemisorption from the B‐Si precipitates formed in the BRL is considered to be one of the possible physical mechanisms involved .…”

Numerical Simulations of IBC Solar Cells Based on Poly-Si Carrier-Selective Passivating Contacts

“…In the first case, pinholes are formed by increasing the annealing temperature above 1000°C in oxide layers above 2 nm [20]. In the second case, the transport of carriers is described by tunneling through a potential energy barrier built by an oxide layer around 1.5 nm thick [22], [30]- [33], implying process temperatures lower than 950°C. It is worth noting that several studies within state-of-the-art complementary metal oxide semiconductor (CMOS) devices [34]- [40] confirm that leakage currents though thin dielectrics are based on tunneling.…”