Direct Digital Synthesizer with 14 GS/s Sampling Rate Heterogeneously Integrated in InP HBT and GaN HEMT on CMOS

Turner, S.E.; Stuenkel, Mark; Madison, Gary M.; Cartwright, Justin; Harwood, Richard L.; Cali, Joseph; Chadwick, S.; Oh, Michael; Matta, John; Meredith, James M.; Byrd, J. M.; Kushner, Lawrence J.

doi:10.1109/rfic.2019.8701821

Cited by 6 publications

(5 citation statements)

References 14 publications

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“…Static frequency dividers are able to offer robust operation over a wide frequency range, playing a critical role in various microwave applications such as quadrature signal generation [1,2,3], phase-locked loop (PLL) [4,5], clock and data recovery (CDR) [6], time-interleaved analog-to-digital converter (ADC) systems [7,8] and other wireless communication fields [9,10]. Applications above generally require frequency division in wide operating bandwidth and at a relatively high rate as their performance continues to evolve, putting forward demands for the design and fabrication of high-speed broadband static frequency dividers.…”

Section: Introductionmentioning

confidence: 99%

A broadband static frequency divider up to 62GHz in InP DHBT with capacitive degeneration

Xiao

Zhen

Cao

et al. 2022

IEICE Electron. Express

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A broadband static frequency divider fabricated in a 165 GHz f t 0.8 µm InP DHBT process is described. Capacitive degeneration technique is adopted, extending the operating bandwidth with little increase in power consumption and area occupancy. The device characteristics are analyzed to achieve high device f t utilization. The chip occupies 0.484 mm×0.44 mm and consumes 380 mW from dual supplies of −2.5 V and −3.5 V. The measured input-referred self-oscillation frequency (SOF) is 56 GHz, and the output power locates in −5.87∼1.87 dBm. With single-ended sinewave input, the divider is operational in 2∼62 GHz, exhibiting a 0.36f t frequency range.

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Section: Introductionmentioning

confidence: 99%

A broadband static frequency divider up to 62GHz in InP DHBT with capacitive degeneration

Xiao

Zhen

Cao

et al. 2022

IEICE Electron. Express

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“…High speed and wide-band frequency dividers are widely used in quadrature signal generation [1,2], time-interleaved THA and ADC systems [3,4,5], and other high-speed communication fields [6]. A number of dividers based on different topologies and processes have been reported so far.…”

Section: Introductionmentioning

confidence: 99%

A broadband high bandwidth utilization ECL static frequency divider in InP DHBT process

Zhen

Cao

et al. 2020

IEICE Electron. Express

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This letter presents a broadband 2:1 static ECL frequency divider in a 0.8 µm InP DHBT process. The proposed divider is based on an ECL double emitter-followers structure. The maximum cut-off frequency ( f t ) utilization of the device is improved up to 0.967 through theoretical analysis and calculation. The measurement shows that the divider can operate with input frequency from 1 GHz to 62 GHz in sinusoidal waveform, while the maximum f t of the device is 150 GHz. Bandwidth utilization BW /f t is 0.413, which is an extremely high value for InP devices at the same size.

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“…Es gibt eine CORDIC(coordinate rotating digital computer)-Technik für DDS mit einer höheren Frequenz. Aufgrund der Anforderung der digitalen Blöcke erfordert die Implementierung eines solchen Codes jedoch einen hohen Stromverbrauch [2]. Andererseits kann der nichtlineare DAC-basierte (ROM-lose) Code auch für Hochgeschwindigkeits-DDS verwendet werden.…”

Section: Dds Architekturunclassified

“…This algorithm calculates the amplitude directly, based on the projection of a rotating vector in a polar axial system [61]. This requires considerable amount of hardware and power consumption, and its implementation is mostly available up to 14 GHz frequency operation [62], [2].…”

Section: Cordic Approach Dds Architecturementioning

confidence: 99%

“…Thus, such techniques are limited to low DDS clock (< 5 GHz) operation. There is a CORDIC technique available for DDS even at 14 GHz however due to the requirement of the digital blocks, to implement such code demands extensive power consumption [2]. Other hands, the non-linear DAC based (ROM-less) can also be used for high-speed DDS, however, it also suffers from extensive power consumption and circuit complexity due to the large number (several hundred) of unit current source needed for weighting the sin wave amplitudes.…”

Section: Chapter 8 Conclusionmentioning

confidence: 99%

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SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization

Shrestha¹

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The requirement of the versatile signal generator has always been evident in modern RF and communication systems. The most conventional technique, voltage control oscillator (VCO), has inferior phase noise and narrow bandwidth despite its operating frequency can be up to the sub-THz regime. Its phase noise influenced by a various parameter associated with the oscillator circuit e.g. transistor size \& noise, bias current, noise leaking from the bias supply etc. The bandwidth is limited because the input voltage \& the output frequency of the VCO is not strictly linear over the tuning range. The phase noise and SFDR of the VCO output are enhanced by using the phase-lock technique. The phase-locked loop (PLL) uses the feedback system locking the reference frequency set by the VCO. However, the settling time of the PLL is higher due to a feedback control loop. The higher settling time increases the frequency switching time between PLL outputs. IG-oscillators is suitable for multi-GHz range and wide bandwidth application. Signal generation can alos be achieved by the free-electron radiation, optical lasers, Gunn diodes as well and they can operate even at the THz domain. All these signal generators suffer from slow frequency switching, lack of digital controllability, and advance modulation capability even though their frequency of operation is THz regime. Alternatively, the AWG (arbitrary wave generator) can produce a wide range of frequencies with low phase noise, including digital controllability. One of the vital components of the AWG is the direct digital synthesiser (DDS). Generally, it is composed of a phase accumulator, digital to analogue converter, sine mapping circuits and low pass filter. It needs a reference clock that acts as samples of the DDS outputs. Its output frequency can be varied by applying an appropriate digital input code. But high-speed DDS has several limitations; such as low number of output frequency points, lack of phase control unit, high power consumptions etc. This work addresses such limitations.

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Direct Digital Synthesizer with 14 GS/s Sampling Rate Heterogeneously Integrated in InP HBT and GaN HEMT on CMOS

Cited by 6 publications

References 14 publications

A broadband static frequency divider up to 62GHz in InP DHBT with capacitive degeneration

A broadband static frequency divider up to 62GHz in InP DHBT with capacitive degeneration

A broadband high bandwidth utilization ECL static frequency divider in InP DHBT process

SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization

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