A broadband high bandwidth utilization ECL static frequency divider in InP DHBT process

Abstract

This letter presents a broadband 2:1 static ECL frequency divider in a 0.8 µm InP DHBT process. The proposed divider is based on an ECL double emitter-followers structure. The maximum cut-off frequency ( f t ) utilization of the device is improved up to 0.967 through theoretical analysis and calculation. The measurement shows that the divider can operate with input frequency from 1 GHz to 62 GHz in sinusoidal waveform, while the maximum f t of the device is 150 GHz. Bandwidth utilization BW /f t is 0.413, which is an extremely high value for InP devices at the same size.

A wideband InP Gilbert-cell mixer using capacitive degeneration and current bleeding technique

“…The maximum operating frequency of a circuit is limited by the device cut-off frequency f t , which means the bandwidth of the mixer can not exceed a section of device f t [25]. It may become a considerable limitation for the bandwidth of the mixer if transistors are biased at a point with much lower f t than the peak f t ( f t ma x ).…”

“…The -3 dB bandwidth is from 0.1 GHz to 49 GHz. The bandwidth utilization (BW/ f t ) [25] and gain-bandwidth product (GBP) [26] achieve 0.306 and 260 GHz respectively, which are excellent performance for wideband mixers.…”

A broadband static frequency divider up to 62GHz in InP DHBT with capacitive degeneration

“…In the CML latch, switch transistors Q 1 are one of the main factors that limit the highest operating frequency, because the signals flowing in them exhibit a 2× f out frequency [27]. To extend bandwidth, the performance of Q 1 needs to be improved as much as possible.…”

“…The simulated time-domain waveforms of i c,7 at 50 GHz input frequency with different C d are shown in Fig. 5(a), where "C d =0 fF, R d =0 Ohm" is the equivalent conventional topology as in [27]. With a larger C d , i c,7 exhibits a higher amplitude at high frequencies, which means a stronger boost to Q 7 .…”

“…This paper puts forward a capacitive degeneration method [25,26], which is first applied in emitter-coupled-logic (ECL) static divider design. Compared with [27], the topology of this work is more innovative. The method extends the bandwidth and improves the performance effectively with little increase in power consumption and area occupancy.…”