Diminished-one modulo 2/sup n/+1 adder design

“…Channel three will be implemented using an inverter, for the one's complement of one operand and a Ling modulo 2 2n+1 -1 adder. Based on the Ling modulo adder [31], estimated area and delay for channel three are 3n + 12n and 2 +3 respectively. We present the decomposition of area and delay of each channel in the tables 2 and 3 respectively.…”

Section: Performance Evaluationmentioning

confidence: 99%

RNS Scaling Algorithm for a New Moduli Set {2^(2n+1) +1, 2^(2n+1), 2^(2n+1)-1}

Mustapha¹,

Bankas²

2017

IJCA

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Scaling is one of the difficult operations in Residue Number System (RNS) and also one of the most important units and a necessary operation used to avoid overflow in RNS based systems. In this paper, a scaling algorithm for a new moduli set {2 2n+1 +1, 2 2n+1 , 2 2n+1 -1} using the Chinese Remainder Theorem (CRT) is presented. In the design of digital systems, the goal of designers is to increase performance and decrease the amount of hardware resources. In order to achieve this, a new moduli sets is proposed to obtain a larger dynamic range and less complex hardware architecture. The CRT is further simplified for the selected moduli set to reduce the hardware complexity of the scaling algorithm. The scaling algorithm does not introduce any scaling errors and thus is efficient. When compared with the state of the art scaling algorithm using the Unit-Gate model, the results show that, the proposed scaling algorithm outperforms the state of the art scaling algorithm in terms of dynamic range (DR), area consumption, and delay by 98%, 18.4% and 21.7% respectively. General TermsModuli Set, Scaling Algorithm, Residue Number System, Chinese Remainder Theorem.

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“…The compressor could be regarded as a novel modulo 2 n + 1 adder since they perform the same operation counting two inputs of the compressor as one operand. For the modulo 2 n + 1 4-2 compressor, the delay is close to a constant and the area is linearly proportional to n. For the modulo 2 n + 1 adder involving an n-bit carry-propagation addition and a zero indicator [1], the delay and the area are approximately proportional to log n and n log n respectively [4]. When n is larger than 8, the compressor requires less delay and area than the adder.…”

Section: Modulo 2 N + 1 4-2 Compressormentioning

confidence: 99%

“…Important operations in the FNT include the butterfly operation (BO) and the code conversion (CC) which are both composed of modulo 2 n + 1 addition mainly. The fastest modulo 2 n + 1 adder involving carry-propagation addition in the diminished-1 number system is proposed by Vergos and used in the recent architectures [4,5,6]. The carry-propagation modulo 2 n + 1 addition makes the existing FNT architectures require large area and delay.…”

Section: Introductionmentioning

confidence: 99%

Area-delay efficient parallel architecture for Fermat number transform

Zhang

2009

IEICE Electron. Express

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Abstract:The parallel Fermat number transform (FNT) architecture is usually implemented with the code conversion (CC) and the butterfly operation (BO) in the diminished-1 number system. However, both the CC and the BO require too much area and delay due to modulo 2 n +1 carry-propagation addition. In this paper, we propose a novel parallel FNT architecture with the root of unity 2 which is mainly composed of carry-save code conversion (CSCC) and carry-save butterfly operation (CSBO). The CSCC and the CSBO remove the carrypropagation addition by exploiting the property of carry-save adders. Thus the proposed FNT architecture requires less area and delay than the previous one. Synthesis results using 0.13-µm CMOS standard cells library demonstrate the superiority of the resulting architecture against the previously reported solution.

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Diminished-one modulo 2/sup n/+1 adder design

Cited by 137 publications

References 17 publications

Unified Approach to the Design of Modulo-(2^n +/- 1) Adders Based on Signed-LSB Representation of Residues

Unified Approach to the Design of Modulo-(2^n +/- 1) Adders Based on Signed-LSB Representation of Residues

RNS Scaling Algorithm for a New Moduli Set {2^(2n+1) +1, 2^(2n+1), 2^(2n+1)-1}

Area-delay efficient parallel architecture for Fermat number transform

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