Digital VLSI using parallel architecture for co-occurrence matrix determination

Ba, Ming Ting; Degrugillier, Dominique; Berrou, Claude

doi:10.1109/icassp.1989.266989

Cited by 2 publications

(2 citation statements)

References 2 publications

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“…Their features enable the development of a hardware system dedicated to performing fast co-occurrence matrix computations, thus meeting the requirements of realtime image analysis applications. On the other hand, the Very Large Scale Integration (VLSI) architectures could be considered as competitive alternatives [9]. However, they are not reconfigurable and they involve high development cost and time-consuming development procedures.…”

Section: Introductionmentioning

confidence: 99%

FPGA architecture for fast parallel computation of co-occurrence matrices

Iakovidis

Maroulis

Bariamis

2007

Microprocessors and Microsystems

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This paper presents a novel architecture for fast parallel computation of cooccurrence matrices in high throughput image analysis applications for which time performance is critical. The architecture was implemented on a XilinxVirtex-XCV2000E-6 FPGA using VHDL. The symmetry and sparseness of the co-occurrence matrices are exploited to achieve improved processing times, and smaller, flexible area utilization as compared with the state of the art. The performance of the proposed architecture is evaluated using input images of various dimensions, in comparison with an optimized software implementation running on a conventional general purpose processor. Simulations of the architecture on contemporary FPGA devices show that it can deliver a speedup of two orders of magnitude over software.

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Section: Introductionmentioning

confidence: 99%

FPGA architecture for fast parallel computation of co-occurrence matrices

Iakovidis

Maroulis

Bariamis

2007

Microprocessors and Microsystems

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“…A dedicated hardware system that efficiently computes co-occurrence matrices in parallel can meet the requirements for real-time image analysis applications. The Very Large Scale Integration (VLSI) architectures [ 10] provide an alternative to the FPGAs, but have drawbacks such as higher cost and time-consuming development. Furthermore, they cannot be reconfigured.…”

Section: Introductionmentioning

confidence: 99%

Dedicated Hardware for Real-Time Computation of Second-Order Statistical Features for High Resolution Images

Bariamis

Iakovidis

Maroulis

2006

Advanced Concepts for Intelligent Vision Systems

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Abstract. We present a novel dedicated hardware system for the extraction of second-order statistical features from high-resolution images. The selected features are based on gray level co-occurrence matrix analysis and are angular second moment, correlation, inverse difference moment and entropy. The proposed system was evaluated using input images with resolutions that range from 512×512 to 2048×2048 pixels. Each image is divided into blocks of userdefined size and a feature vector is extracted for each block. The system is implemented on a Xilinx VirtexE-2000 FPGA and uses integer arithmetic, a sparse co-occurrence matrix representation and a fast logarithm approximation to improve efficiency. It allows the parallel calculation of sixteen co-occurrence matrices and four feature vectors on the same FPGA core. The experimental results illustrate the feasibility of real-time feature extraction for input images of dimensions up to 2048×2048 pixels, where a performance of 32 images per second is achieved.

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Digital VLSI using parallel architecture for co-occurrence matrix determination

Cited by 2 publications

References 2 publications

FPGA architecture for fast parallel computation of co-occurrence matrices

FPGA architecture for fast parallel computation of co-occurrence matrices

Dedicated Hardware for Real-Time Computation of Second-Order Statistical Features for High Resolution Images

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