FPGA architecture for fast parallel computation of co-occurrence matrices

Abstract

This paper presents a novel architecture for fast parallel computation of cooccurrence matrices in high throughput image analysis applications for which time performance is critical. The architecture was implemented on a XilinxVirtex-XCV2000E-6 FPGA using VHDL. The symmetry and sparseness of the co-occurrence matrices are exploited to achieve improved processing times, and smaller, flexible area utilization as compared with the state of the art. The performance of the proposed architecture is evaluated using input images of various dimensions, in comparison with an optimized software implementation running on a conventional general purpose processor. Simulations of the architecture on contemporary FPGA devices show that it can deliver a speedup of two orders of magnitude over software.

Parallel implementation of Gray Level Co-occurrence Matrices and Haralick texture features on cell architecture

“…Although the computational complexity of the co-occurrence matrix for an image of size N ×N is only O(N 2 ), the computational power requirements to compute multiple co-occurrence matrices, which are needed in many applications such as medical image processing are significantly large [11].…”

“…Many researchers have been working on accelerating the process of computation the GLCMs and texture features extraction algorithms on FPGAs platforms [5,11,[14][15][16][17]. Tahir [5] presented an FPGA-based coprocessor for GLCM and texture features and their application in prostate cancer classification.…”

“…Iakovidis et al [11] presented an FPGA architecture for parallel computation of 16 co-occurrence matrices (d = 1, 2, 3, 4) and (θ = 0, 45, 90, 135) that exploits both their symmetry and sparseness. They used 5-bit gray-level representation just like [15].…”

“…First, some implementations such as [5] required large external memory banks, while some processing is performed by a host machine. Second, other implementations such as [11,15] included symmetry and sparseness matrices, which is not a general implementation to support all kinds of images. Finally, these implementations calculate GLCMs without implementation considerations for improving the performance of the Haralick texture features.…”

The Modeling and Hardware Implementation of Semiconductor Circuit Elements by Using ANN and FPGA

“…FPGAs have many consistent advantages such as reliable, flexible, fast response rapid prototyping, adaptation, reduced cost, simplicity of design and programmable architecture [1][2][3]. FPGA model can be easily reprogrammed and is completely customizable.…”