Digital System Test and Testable Design

Abstract

), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights.Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) This book is dedicated to my wife, Irma, and sons Aarash and Arvand. wwwwwwwwwwww vii This is a book on test and testability of digital circuits in which test is spoken in the language of design. In this book, the concepts of testing and testability are treated together with digital design practices and methodologies. We show how testing digital circuits designing testable circuits can take advantage of some of the well-established RT-level design and verification methodologies and tools. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. In the testability part, it describes various scan and BIST methods in Verilog and uses Verilog testbenches as virtual testers to examine and evaluate these testability methods. In designing testable circuits, we use Verilog testbenches to evaluate, and thus improve testability of a design.The first part of the book develops Verilog test environments that can perform gate-level fault simulation and test generation. This part uses Verilog PLI along with Verilog's powerful testbench development facilities for modeling hardware and programing test environments. The second part of the book uses Verilog as a hardware design tool for describing DFT and BIST hardware. In this part, Verilog is used as a hardware description language describing synthesizable testable hardware. Throughout the book, Verilog simulation helps developing and evaluating test methods and testability hardware constructs.This book professes a new approach to teaching test. Use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. As HDLs were used in late 1970s for teaching computer architectures, today, HDLs can be used to illustrate test methodologies and testability architectures that are otherwise illustrated informally by flow charts, graphs, and block diagrams. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing on-chip test hardware in Verilog helps evaluating the related algorithms in terms of hardware overhead and timing and thus feasibility of using them on SoC chips. Further support for this approach comes in use of testbenches. Using PLI in developing testbenches and virtual testers gives us a powerful progra...

Turbo-charging Lemmas on demand with don't care reasoning

“…In the context of ATPG [18], sets of don't care conditions are usually divided into observability don't cares (ODC) and controllability don't cares (CDC). The former denotes lines that do not influence the primary outputs (independent from the current assignment to the primary inputs), and the latter identifies line values that can not be justified and are therefore illegal under any assignment to the primary inputs.…”

“…We show that don't care reasoning on full candidate models to extract partial candidate models subsequently reduces the cost for consistency checking by focusing on the relevant parts of the formula, only. Motivated by dual propagation techniques in the context of quantified boolean formulas (QBF) [15] [16], we propose an optimization of the lemmas on demand procedure in [19] and compare our approach to a technique based on justification heuristics in ATPG [18]. We implemented both techniques in our SMT solver Boolector and analyse the results in comparison to the version of Boolector that won the QF AUFBV track of the SMT competition 2012.…”

Yield Modeling for Error Tolerant and Partially Defect Tolerant Arrays

“…Fault models describe physical defects and system failures, as well as the input patterns that expose them. Thus, the fault models are suitable for further modeling and testing, while error models describe the effects of defects on the system's outputs, and they are useful for on-line error detection [3].…”

“…Typical yield models are mathematically and/or simulation based. However, in order to provide an accurate estimate of the yield, the model must account various considerations [3]. Redundancy was first introduced for hardware fault-tolerance with Triple Modular Redundancy (TMR) in which the original nonfault-tolerant circuit module was triplicated with majority voting circuits added at the outputs of the triplicated circuit modules [4].…”

An off-line MDSI interconnect BIST incorporated in BS 1149.1

“…But authors in [1] have shown that these fault models do not present enough fault coverage, and proposed MDSI fault model with higher coverage. An accepted cost effective way of testing SoCs is the IEEE std.1149.1 boundary scan standard [2]. One of the drawbacks of using this method is the inability of detecting timing related faults.…”