An off-line MDSI interconnect BIST incorporated in BS 1149.1

Mohammadi, Melika Haji; Sadeghi-Kohan, Somayeh; Masoumi, Nasser; Navabi, Zainalabedin

doi:10.1109/ets.2014.6847847

Cited by 5 publications

(2 citation statements)

References 4 publications

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“…Both approaches use LFSRs for pattern generation. Deterministic approaches for advanced fault models integrate tests based on the MT and the MDSI model [32,56].…”

Section: B Interconnect Bistmentioning

confidence: 99%

“…Here specific defect and aging mechanisms such as crosstalk or electromigration (EM) must be addressed, which can manifest themselves for example as delay faults or glitches at the gate level. In this context, the BIST and monitoring schemes proposed in [4,11,17,32,34,36,37,41,47,49,55,56], focus on manufacturing test, but they do not address the requirements and challenges of health monitoring during the lifetime. Nevertheless, because of the complex interplay between EM and crosstalk, periodic testing of interconnects is mandatory and at the same time Communicated by S. N. Demidenko extremely challenging.…”

Section: Introductionmentioning

confidence: 99%

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Stress-Aware Periodic Test of Interconnects

2021

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Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.

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“…Both approaches use LFSRs for pattern generation. Deterministic approaches for advanced fault models integrate tests based on the MT and the MDSI model [32,56].…”

Section: B Interconnect Bistmentioning

confidence: 99%