Digital Predistortion for 5G Small Cell: GPU Implementation and RF Measurements

Abstract

In this paper, we present a high data rate implementation of a digital predistortion (DPD) algorithm on a modern mobile multicore CPU containing an on-chip GPU. The proposed implementation is capable of running in real-time, thanks to the execution of the predistortion stage inside the GPU, and the execution of the learning stage on a separate CPU core. This configuration, combined with the low complexity DPD design, allows for more than 400 Msamples/s sample rates. This is sufficient for satisfying 5G new radio (NR) base station radio transmission specifications in the sub-6 GHz bands, where signal bandwidths up to 100 MHz are specified. The linearization performance is validated with RF measurements on two base station power amplifiers at 3.7 GHz, showing that the 5G NR downlink emission requirements are satisfied.

Linearization as a Solution for Power Amplifier Imperfections: A Review of Methods

“…One of the examples of such a problem is the delay time due to finite speed of processor calculations and its relation to maximal network latency (which is defined as time it takes data to travel from one point to another) of less than 1 ms in 5G, which we mentioned in the introduction. In [93][94][95], the delay of DPD, depending on the implementation (FPGA, GPU, ASIC), is evaluated to be tens to hundreds of microseconds. Taking into account the fact that signal may have to pass through multiple DPD stages and through the whole data transfer system, it is possible DPD delay will be a major bottleneck in overall system latency.…”