Digital lock detector for PLL

Melikyan, Vazgen; Hovsepyan, Aristakes; Ishkhanyan, Mkrtich; Hakobyan, Tigran

doi:10.1109/ewdts.2008.5580147

Cited by 7 publications

(3 citation statements)

References 7 publications

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“…However, if the clock frequency is out of the required ppm, then it switches the loop to frequency tracking loop. In conventional lock detector [23], two N-bit counters are clocked by a reference clock (REF) and a VCO clock after divider (DIV) respectively. After every cycle of DIV, the state of both counters will be compared by a D-flip-flop (DFF) to provide a LOCK signal that determine whether the frequency is locked or not.…”

Section: F Lock Detectormentioning

confidence: 99%

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

Tan

Yeo

Boon

et al. 2012

IEEE Trans. Circuits Syst. I

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This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18-CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply.Index Terms-Charge Pump, Clock and Data Recovery (CDR), dual-loop, lock detector, Phase Detector (PD), quarter-rate architecture, 5-Gb/s.

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Section: F Lock Detectormentioning

confidence: 99%

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

Tan

Yeo

Boon

et al. 2012

IEEE Trans. Circuits Syst. I

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“…The lock detector (LD) [1] in a dual-loops CDR [2,3] acts as a vital role to control the switching between the loops. One of the problems in the conventional LD architecture is that there is only one required ppm to switch between frequency tracking loop and phase tracking loop [4].…”

Section: Introductionmentioning

confidence: 99%

Design of a hysteresis lock detector for dual-loops clock and data recovery circuit

Tan

Yeo

Boon

et al. 2011

2011 IEEE International Conference of Electron Devices and Solid-State Circuits

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In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm will leads to a longer lock time for phase tracking loop and small ppm will leads to more switching time between the loops. A novel lock detector with hysteresis property is proposed in this paper. It provides two different ppms in both different conditions; a smaller ppm for in-lock condition and a larger ppm for out-of-lock condition. This paper also provides a detailed analysis of the proposed lock detector at different conditions. The proposed lock detector is simulated in 0.18-um technology and it consumes 1.1-mW at a 1.8V supply voltage.Index Terms -dual-loops clock and data recovery circuit, frequency lock detector, hysteresis property.

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“…In dual-loop CDR architecture, the lock detector (LD) [108,109] acts as a vital role to control the switching between the frequency acquisition loop and the phase tracking loop. Initially, as the frequency of the VCO is further away from the operating frequency, the LD will enable the frequency acquisition loop.…”

Section: The Proposed Lock Detector (Ld)mentioning

confidence: 99%

Design of a high speed and power efficient quarter-rate clock and data recovery circuit

Tan¹

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Due to the advantage in technology and multi-media, the demand for data communication has increased tremendously. More standards for high speed low power communication have been established, i.e. Serial Advanced-Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB) and etc. In the receiver design, the clock and data recovery (CDR) circuit is an important block as the clock signal is embedded in the receiving data. This thesis presents several new circuit designs to improve the performance of the CDR circuit. First, a new quarter-rate linear phase detector (PD) is proposed to reduce the circuit complexity of the reported quarter-rate linear PD design. Besides that, the proposed PD applies UP pulse-widening technique to resolve the issue of small UP pulses. The existing PDs with UP pulse-widening techniques have more output signals, which increases the difficulties in designing the Charge Pump (CP). In the proposed PD, the number of output signals has been successfully minimized. This thesis also provides propagation delay analysis of the proposed PD. A set of equations is derived from the analysis to predict the characteristic curve of the proposed PD. At the linear region, the accuracy of the prediction results is 98% of the simulation results. The effect on propagation delay at various phase differences is also being discussed.

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Digital lock detector for PLL

Cited by 7 publications

References 7 publications

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

Design of a hysteresis lock detector for dual-loops clock and data recovery circuit

Design of a high speed and power efficient quarter-rate clock and data recovery circuit

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