Digital Background Calibration With Histogram of Decision Points in Pipelined ADCs

Gholami, Peyman; Yavari, Mohammad

doi:10.1109/tcsii.2017.2660765

Cited by 17 publications

(9 citation statements)

References 11 publications

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“…Owing to use of Newton–Raphson algorithm instead of commonly used least mean square algorithm, the digital complexity of the proposed method is less than Montazerolghaem et al (2015). The convergence time of the proposed method is relatively less than the digital window (Sun and Wu, 2018), histogram-based technique (Gholami and Yavari, 2017) and the statistical-based approach (Mafi et al , 2018). Furthermore, the proposed method is not dependent on the statistic of the input signal as histogram-based (Gholami and Yavari, 2017) and statistical-based approach (Mafi et al , 2018).…”

Section: Simulation Resultsmentioning

confidence: 99%

“…The convergence time of the proposed method is relatively less than the digital window (Sun and Wu, 2018), histogram-based technique (Gholami and Yavari, 2017) and the statistical-based approach (Mafi et al , 2018). Furthermore, the proposed method is not dependent on the statistic of the input signal as histogram-based (Gholami and Yavari, 2017) and statistical-based approach (Mafi et al , 2018). While the maximum input bandwidth is limited (Zia et al , 2019) because of spline interpolation filter, the proposed method does not have this limitation.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…The normal operation of the pipelined ADCs is interrupted in foreground calibrations while background techniques continuously detects and removes the errors. The most popular digital background calibration methods are categorized into histogram-based (Brooks and Lee, 2008; Gholami and Yavari, 2017), statistical-based (Mafi et al , 2018; Mafi et al , 2016), correlation-based (Panigada and Galton, 2006; Panigada and Galton, 2009) and deterministic (McNeill et al , 2009; Sarkar et al , 2015; Sehgal et al , 2015; Montazerolghaem et al , 2015; Zia et al , 2019). The priority of deterministic techniques over others is the faster calibration time.…”

Section: Introductionmentioning

confidence: 99%

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New digital background calibration method for pipelined ADCs

Zia

Farshidi

Kosarian

2020

COMPEL

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Purpose Pipelined analog-to-digital converters (ADCs) are widely used in electronic circuits. The purpose of this paper is to propose a new digital background calibration method to correct the capacitor mismatch, finite direct current (DC) gain and nonlinearity of residue amplifiers in pipelined ADCs. Design/methodology/approach The errors are corrected by defining new functions based on generalized Newton–Raphson algorithm. Although the functions have analytical solutions, an iterative procedure is used for calibration. To accelerate the calibration process, proper initialization for the errors is identified by using evaluation estimation block and solving inverse matrix. Findings Several behavioral simulations of a 12-bit 100MS/s pipelined ADC in MATLAB indicate that signal-to-(noise + distortion) ratio (SNDR) and spurious free dynamic range (SFDR) are improved from 30dB/33dB to 70dB/79dB after calibration. Calibration is achieved in approximately 2,000 clock cycles. Practical implications The digital part of the proposed method is implemented on field-programmable gate array to validate the performance of the pipelined ADC. The experimental result shows that the degradation of SNDR, SFDR, integral nonlinearity, differential nonlinearity and effective number of bits is negligible according to fixed-point operation vs floating-point in simulation results. Originality/value The novelty of this study is to use Newton–Raphson algorithm combined with appropriate initialization to reduce the number of divisions as well as calibration time, which is suitable in the recent nano-meter complementary metal oxide semiconductor technologies.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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New digital background calibration method for pipelined ADCs

Zia

Farshidi

Kosarian

2020

COMPEL

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“…However, employing of many sub-stages to meet high resolution requirement will certainly lead to higher circuit complexity, and therefore high-power consumption and large occupied area. In order to improve the accuracy of pipelined ADC, Gholami et al [55] proposed a digital background calibration technology called decision point histogram (DPH) correction (as shown in Figure 13a). The capacitor mismatch and residual amplifier gain error can be corrected by estimating the output codes of the decision points in the residual characteristics.…”

Section: Pipelined Adcmentioning

confidence: 99%

“…The prototype chip occupies less than 4 mm 2 of silicon area and dissipates a total power of 330 mW from a 2.5 V supply. To improve SNR of ADC, Wang et al [57] proposed a 12-bit pipelined ADC using an open-loop residual amplifier based on the first In order to improve the accuracy of pipelined ADC, Gholami et al [55] proposed a digital background calibration technology called decision point histogram (DPH) correction (as shown in Figure 13a). The capacitor mismatch and residual amplifier gain error can be corrected by estimating the output codes of the decision points in the residual characteristics.…”

Section: Pipelined Adcmentioning

confidence: 99%

A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System

et al. 2022

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As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.

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A new background continuous‐time offset cancelation and gain calibration strategy for open‐loop residue amplifiers in high‐speed and high‐resolution ADC's

Ghasemzadeh

Hadidi

2022

Circuit Theory & Apps

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A continuous-time offset cancelation and gain calibration strategy is proposed for open-loop residue amplifiers of pipeline ADC's. Utilizing a reliable technique for detecting gain and offset error, also saving digital amounts of the signals that are resulted from the calibration loop, data conversion proceeds without any interruption. In addition, due to sharing this structure between the several RA stages in ADC, power consumption and area occupation are decreased. Also, this strategy does not require extra circuits, like replica residue amplifier or wide-bits digital processor for offset and gain-error correction.Using digital circuits results in multiplexing clock frequency; also, utilizing a unit gain and offset calibration structure for the whole RA in the main ADC results in a significant power consumption reduction. The simulations show that the input-referred offset is reduced to around 30 μV. Also, the gain calibration loop provides a gain of 8 with an error deviation less than 0.001. Postlayout simulation results are presented at all process corners and various temperatures, using HSPICE software and 0.18 μm standard CMOS technology in 14-bit 200 MS/s Pipeline ADC with 23 dB improvement in SNR and 3.9 bit in ENOB.

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Digital Background Calibration With Histogram of Decision Points in Pipelined ADCs

Cited by 17 publications

References 11 publications

New digital background calibration method for pipelined ADCs

New digital background calibration method for pipelined ADCs

A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System

A new background continuous‐time offset cancelation and gain calibration strategy for open‐loop residue amplifiers in high‐speed and high‐resolution ADC's

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