Digit-serial design of a wave digital filter

Hu, Ming; Vainio, Olli; Renfors, Markku

doi:10.1109/imtc.1999.776810

Cited by 3 publications

(1 citation statement)

References 11 publications

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“…Also the general-order lossless and discrete integrator/ differentiator methods were involved. In low-powerfilter implementation, digit-serial computation showed to be advantageous compared to bit-serial and parallel arithmetic [5]. The digital-serial processing elements are obtained using unfolding techniques.…”

Section: Introductionmentioning

confidence: 99%

VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

Mack¹,

Rizkalla²,

Salama³

et al. 2010

WSN

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A low power model for Code Division Multiple Access (CDMA) based cellular communication system is developed. The dynamic power is minimized by reducing the frequency of the Phase Lock Loop (PLL) after lock is established. The paper addresses the feasibility of lowering the clock frequency of the processing unit that models the PLL is addressed and modulator/demodulator functions of the system while maintaining synchronization with the memory unit and other peripherals. The system is simulated with Matlab considering various Signal-to-Noise Ratios (SNR). For a given SNR, the minimum frequency required for the PLL to maintain lock is determined. The Matlab file is translated to VHDL code, simulated and synthesized with Mentor tools, and the layout then generated. Mach-Pa 5-V software system from Mentor tools is utilized to estimate the power consumed by the simulated device. A Xilinx file is also generated and downloaded for Field Programmable Gate Arrays (FPGA) implementation. A 50 MHz clock frequency of the processing unit was first considered and then lowered to 20 MHz for the low power study. Lowering the base and clock frequency resulted in near 30% reduction in power

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Section: Introductionmentioning

confidence: 99%

VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

Mack¹,

Rizkalla²,

Salama³

et al. 2010

WSN

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Digit-serial implementation of LDI/LDD allpass filters

Landernäs

Holmberg

Harnefors

et al.

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

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In this paper we study digit-serial implementation of the general-order lossless discrete integrator/differentiator (LDI/LDD) allpass filter structure. In low-power filter implementation, digit-serial computation has been shown to be advantageous compared to bit-serial and parallel arithmetics [l]. The digit-serial processing elements are obtained using unfolding techniques. The implementation is compared to a corresponding wave digital (WD) implementation. It is shown in an example that a WD realization requires about 60% and 30% more D flip-flops for pipelining and shimming delays, respectively, than the corresponding LDI/LDD implementation. We also study the sample period of the second-order LDI/LDD allpass filter using different digit sizes and conclude that when the filter is scheduled over a number of sample periods we achieve the shortest sample period.

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A Systematic Algorithm for the Design of Lattice Wave Digital Filters With Short-Coefficient Wordlength

Yli‐Kaakinen¹,

Saramäki

2007

IEEE Trans. Circuits Syst. I

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This paper describes an efficient algorithm for designing lattice wave digital (LWD) filters (parallel connections of two all-pass filters) with short-coefficient wordlength. The coefficient optimization is performed using the following three steps. First, an initial infinite-precision filter is designed such that it exceeds the given criteria in order to provide some tolerance for coefficient quantization. Second, a nonlinear optimization algorithm is used for determining a parameter space of the infinite-precision coefficients including the feasible space where the filter meets the given criteria. The third step involves finding the filter parameters in this space so that the resulting filter meets the given criteria with the simplest coefficient representation forms. The proposed algorithm guarantees that the optimum finite-precision solution can be found for both the fixed-point binary and multiplierless coefficient representation forms. In addition, this algorithm is applicable for producing the desired finite-precision solutions for both conventional and approximately linear-phase LWD filters. Comparisons with some other existing quantization schemes show that the proposed algorithm gives the best finite-precision solutions in all examples taken from the literature.Index Terms-Recursive digital filters, coefficient quantization, finite precision, multiplierless implementations, lattice wave digital (LWD) filters, optimization, parallel connection of all-pass filters, approximately linear-phase recursive filters, very large-scale integration (VLSI) implementations.

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Digit-serial design of a wave digital filter

Cited by 3 publications

References 11 publications

VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

Digit-serial implementation of LDI/LDD allpass filters

A Systematic Algorithm for the Design of Lattice Wave Digital Filters With Short-Coefficient Wordlength

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