Digit-serial implementation of LDI/LDD allpass filters

Landernäs, Krister; Holmberg, J.; Harnefors, Lennart; Vesterbacka, Mark

doi:10.1109/iscas.2002.1011445

Cited by 2 publications

(1 citation statement)

References 5 publications

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“…At later stage, it was utilized for designing switchedcurrent filters [36,37] and switched-capacitor sigmadelta AD converters [38]. For example, the LDI transform is used for designing digital filters with low complexity coefficients in [39], Lossless Discrete Differentiator (LDD) in [40], and digital allpass filters in [41].…”

Section: Introductionmentioning

confidence: 99%

Inversion of Shortened LDI Matrix for Designing Discrete-time Filters

Biolek¹,

Kuben²

2014

KMUTNB: IJAST

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The paper deals with the problem of the inversion of the so-called shortened LDI matrix for conversion between the coefficients of continuous-time and discrete-time linear filters whose sand z-domain transfer functions are coupled via LDI transform. The elements of the inverse matrix are expressed by analytic formulae for general order of the matrix. The corresponding mathematical proofs are given.

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Section: Introductionmentioning

confidence: 99%

Inversion of Shortened LDI Matrix for Designing Discrete-time Filters

Biolek¹,

Kuben²

2014

KMUTNB: IJAST

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VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

Mack¹,

Rizkalla²,

Salama³

et al. 2010

WSN

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A low power model for Code Division Multiple Access (CDMA) based cellular communication system is developed. The dynamic power is minimized by reducing the frequency of the Phase Lock Loop (PLL) after lock is established. The paper addresses the feasibility of lowering the clock frequency of the processing unit that models the PLL is addressed and modulator/demodulator functions of the system while maintaining synchronization with the memory unit and other peripherals. The system is simulated with Matlab considering various Signal-to-Noise Ratios (SNR). For a given SNR, the minimum frequency required for the PLL to maintain lock is determined. The Matlab file is translated to VHDL code, simulated and synthesized with Mentor tools, and the layout then generated. Mach-Pa 5-V software system from Mentor tools is utilized to estimate the power consumed by the simulated device. A Xilinx file is also generated and downloaded for Field Programmable Gate Arrays (FPGA) implementation. A 50 MHz clock frequency of the processing unit was first considered and then lowered to 20 MHz for the low power study. Lowering the base and clock frequency resulted in near 30% reduction in power

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Digit-serial implementation of LDI/LDD allpass filters

Cited by 2 publications

References 5 publications

Inversion of Shortened LDI Matrix for Designing Discrete-time Filters

Inversion of Shortened LDI Matrix for Designing Discrete-time Filters

VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

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