Differential vias transition modeling in a multilayer printed circuit board

Cocchini, Matteo; Cheng, Wei; Zhang, Jianmin; Fisher, John; Fan, Jun; Drewniak, James L.; Zhang, Yaojiang

doi:10.1109/isemc.2008.4652164

Cited by 13 publications

(7 citation statements)

References 2 publications

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“…The reason to use FVT for optimization is that FVT is much fast when compared to the full-wave optimization, which takes 20 times longer [7]. Details including algorithms and applications on FVT can be found in [8]- [11]. GUI (Graphic User Interface) of the tool is shown in Fig.…”

Section: A Optimization and Parameter Extrapolation Using A Fastmentioning

confidence: 99%

Signal transition structure optimization for 16 Gbps SFP cage and PCB interface

Zhang

Wang

Lim

et al. 2011

2011 IEEE International Symposium on Electromagnetic Compatibility

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SFP (Small Form-factor Pluggable) module and SFP cage form an interface between a network device and an optic cable or a copper cable for data communication and telecommunication. Data rate on such an interface for a highspeed channel varies from 1 Gbps (Gigabit per second) to 10 Gbps for the existing products, and products with the data rate of 16 Gbps are under development. Due to the differences of networking platform, data rate, and channel length, this interface can be directly driven by an ASIC (Application-Specific Integrated Circuit) or an EDC (Electric Dispersion Compensation) chip in electric domain. Compliance tests are enforced on the interface to fulfil the interoperability requirement, which makes the signal integrity work extremely challenge at 16 Gbps. Since the discontinuity on the interface of a PCB (Printed Circuit Board) and a SFP cage is dominant in the electric path, optimization such an interface structure is critical to meet the compliance specification and achieve system BER (Bit Error Rate). In this paper, a fast via tool is used initially for quick solution about the interface structure optimization. The optimized parameter is verified in a full-wave modelling, and the via structure related resonance is observed and identified. Based on the given SFP cage footprint and observed resonance, a new signal transition structure for the SFP cage and PCB interface is finally proposed, modelled and optimized.

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Section: A Optimization and Parameter Extrapolation Using A Fastmentioning

confidence: 99%

Signal transition structure optimization for 16 Gbps SFP cage and PCB interface

Zhang

Wang

Lim

et al. 2011

2011 IEEE International Symposium on Electromagnetic Compatibility

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show abstract

“…The physical concepts of the method are clear, the simulation is fast, and it is suitable for Spice simulators. Zhang and Fan have done related researches aimed at the method [7][8][9][10][11][12]. Their modeling adopts the first-order capacitance circuit model combined with the impedance characteristics of power/ground plane pair in the center of via.…”

Section: Introductionmentioning

confidence: 99%

“…In [7], a physics-based via-plane model combined with transmission lines models for traces is used. Differential via transition measurements are presented and compared with simulations results of an equivalent circuit model.…”

Section: Introductionmentioning

confidence: 99%

A Novel Segmented Modeling Method of Via including the Effect of Power/Ground Plane Pair

Yan

Shi

et al. 2013

International Journal of Antennas and Propagation

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This paper focuses on the modeling method of common interconnects which act as coupling channels in the analysis of PCB immunity. Fast modeling and parameters extraction of power/ground plane pair are realized using cavity resonance method. The calculated results of the model match with the simulation results of HFSS within 9 GHz, which demonstrates the effectiveness of the modeling method. Besides, segmented via modeling method including the effect of power/ground plane pair is proposed. In this modeling method, via structure is decomposed into three parts, and each part is modeled, respectively. The modeling of single via and differential vias in single plane pair and multilayer is completed using this method. High accuracy is reached due to the adoption of the effect of power/ground plane pair and the adoption of second-order circuit model of capacitance and inductance, where the parameters can be gotten from analytic formulas. Finally, considering an actual signal network, for example, the equivalent circuit model of the network, is established, and every part of the equivalent circuit model is imported into Designer for cosimulation. The results are consistent with the simulation results of HFSS within 9 GHz.

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“…To design a channel including packages at both ends of the channel at such a data rate is challenge due to the discontinuities inside the packages, PCB-package interfaces, and the via transitions for DC blocking capacitors [1]- [6]. Channel lengths are restricted due to the copper loss and the dielectric loss, where the former is proportional to the square root of frequency and the latter is directly proportional to the frequency, and low loss substrate materials of a PCB may have to be used.…”

Section: Introductionmentioning

confidence: 99%

Design and modeling for chip-to-chip communication at 20 Gbps

Zhang

Chen

Qiu

et al. 2010

2010 IEEE International Symposium on Electromagnetic Compatibility

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This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.978-1-4244-6307-7/10/$26.00 ©2010 IEEE

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Differential vias transition modeling in a multilayer printed circuit board

Cited by 13 publications

References 2 publications

Signal transition structure optimization for 16 Gbps SFP cage and PCB interface

Signal transition structure optimization for 16 Gbps SFP cage and PCB interface

A Novel Segmented Modeling Method of Via including the Effect of Power/Ground Plane Pair

Design and modeling for chip-to-chip communication at 20 Gbps

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