Design and modeling for chip-to-chip communication at 20 Gbps

Abstract

This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.978-1-4244-6307-7/10/$26.00 ©2010 IEEE

Design Criteria and Error Sensitivity of Time-Domain Channel Characterization (TCC) for Asymmetry Fixture De-Embedding

“…An equivalent lumped model based on a physical shape and material using a 2-D/3-D tool is the most popular and the fastest way to build the channel model [1], [2], [3]. This simple circuit model, consisting of a resistor, capacitor, and inductor, can be used for the simulation in time domain to predict the system budget and is applicable for de-embedding as a postprocess in frequency domain.…”

Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances

“…Data rates near 10 Gb/s per line are currently achieved using decision-feedback equalization (DFE) with a power consumption of about 1 mW/Gb/s [3][4][5][6][7]. Recent research (e.g., [7][8][9][10]) deals with increasing this speed up to 25 Gb/s per line, whereas speeds up to 100 Gb/s per line are targeted in the (near) future [11].…”