Stub length prediction for back-drilled vias using a fast via tool

Zhang, Jianmin; Chen, Qinghua B.; Wang, Hanfeng; Fan, Jun; Orlandi, Antonio; Drewniak, James L.

doi:10.1109/edaps.2010.5683010

Cited by 7 publications

(2 citation statements)

References 8 publications

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“…In response, a variety of techniques have been developed, including using back drilling to reduce stub length and placing the glass cloth at an oblique angle to reduce unevenness, etc. [4][5][6][7] However, these techniques are neither sufficient to completely eliminate the via stub, nor the skew between the differential wiring. Therefore, with the aim of realizing a transmission configuration that is both stub-less and skew-free, we developed a novel transmission configuration, whereby a flexible printed circuit (FPC) dedicated to high-speed transmission was created and connected with the PKG by a solder bump (Fig.…”

Section: Introductionmentioning

confidence: 99%

Configuration for High-speed Transmission between Flip-chip Packages Using Low Loss and Flexible Substrate

Akahoshi

Mizutani

Sugimoto

et al. 2018

Transactions of The Japan Institute of Electronics Packaging

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To meet the demand for higher signal transmission speeds, we investigated an interconnect structure using a flexible printed circuit (FPC), and clarified that this facilitated major improvements in the signal integrity. A differential transmission line with a stripline structure was created within the FPC, and by connecting this with the IC packages (PKG) via solder bumps, a stub-less, skew-free interconnect configuration was realized. We evaluated 14 Gbps to 56 Gbps electrical characteristics with a prototype module, and verified that this facilitated a 30% to 60% extension of transmission length compared to a conventional printed circuit board (PCB).

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Section: Introductionmentioning

confidence: 99%

Configuration for High-speed Transmission between Flip-chip Packages Using Low Loss and Flexible Substrate

Akahoshi

Mizutani

Sugimoto

et al. 2018

Transactions of The Japan Institute of Electronics Packaging

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“…One method to decrease the discontinuities at the BGA/PCB interface is to perform chip-package-board co-design, so that the impedance in the entire signal path from die to board to another die changes smoothly instead of designing 100 Ω differential impedance for different segmentations independently [4]. As for the DC blocking via structure optimization, detailed work has been done and reported in [5], [6].…”

Section: Introductionmentioning

confidence: 99%

Signal transition structure optimization for 16 Gbps SFP cage and PCB interface

Zhang

Wang

Lim

et al. 2011

2011 IEEE International Symposium on Electromagnetic Compatibility

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SFP (Small Form-factor Pluggable) module and SFP cage form an interface between a network device and an optic cable or a copper cable for data communication and telecommunication. Data rate on such an interface for a highspeed channel varies from 1 Gbps (Gigabit per second) to 10 Gbps for the existing products, and products with the data rate of 16 Gbps are under development. Due to the differences of networking platform, data rate, and channel length, this interface can be directly driven by an ASIC (Application-Specific Integrated Circuit) or an EDC (Electric Dispersion Compensation) chip in electric domain. Compliance tests are enforced on the interface to fulfil the interoperability requirement, which makes the signal integrity work extremely challenge at 16 Gbps. Since the discontinuity on the interface of a PCB (Printed Circuit Board) and a SFP cage is dominant in the electric path, optimization such an interface structure is critical to meet the compliance specification and achieve system BER (Bit Error Rate). In this paper, a fast via tool is used initially for quick solution about the interface structure optimization. The optimized parameter is verified in a full-wave modelling, and the via structure related resonance is observed and identified. Based on the given SFP cage footprint and observed resonance, a new signal transition structure for the SFP cage and PCB interface is finally proposed, modelled and optimized.

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