Differential current-mode clock distribution

Islam, Riadul; Fahmy, Hany; Lin, Ping-Yao; Guthaus, Matthew R.

doi:10.1109/mwscas.2015.7282042

Cited by 8 publications

(5 citation statements)

References 12 publications

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“…The predominant catalyst for this increased attention is the energy-efficient operation characteristic of these networks, as highlighted in [ 10 ]. This aspect distinguishes SNNs from traditional low-power techniques, as documented in various studies [ 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 ]. SNN models are inherently reactive to event-based data, making them particularly apt for address-event representation-based computations, as explored in [ 22 ].…”

Section: Introductionmentioning

confidence: 99%

Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks

Islam,

Majurski,

Kwon

et al. 2024

Sensors

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Organizations managing high-performance computing systems face a multitude of challenges, including overarching concerns such as overall energy consumption, microprocessor clock frequency limitations, and the escalating costs associated with chip production. Evidently, processor speeds have plateaued over the last decade, persisting within the range of 2 GHz to 5 GHz. Scholars assert that brain-inspired computing holds substantial promise for mitigating these challenges. The spiking neural network (SNN) particularly stands out for its commendable power efficiency when juxtaposed with conventional design paradigms. Nevertheless, our scrutiny has brought to light several pivotal challenges impeding the seamless implementation of large-scale neural networks (NNs) on silicon. These challenges encompass the absence of automated tools, the need for multifaceted domain expertise, and the inadequacy of existing algorithms to efficiently partition and place extensive SNN computations onto hardware infrastructure. In this paper, we posit the development of an automated tool flow capable of transmuting any NN into an SNN. This undertaking involves the creation of a novel graph-partitioning algorithm designed to strategically place SNNs on a network-on-chip (NoC), thereby paving the way for future energy-efficient and high-performance computing paradigms. The presented methodology showcases its effectiveness by successfully transforming ANN architectures into SNNs with a marginal average error penalty of merely 2.65%. The proposed graph-partitioning algorithm enables a 14.22% decrease in inter-synaptic communication and an 87.58% reduction in intra-synaptic communication, on average, underscoring the effectiveness of the proposed algorithm in optimizing NN communication pathways. Compared to a baseline graph-partitioning algorithm, the proposed approach exhibits an average decrease of 79.74% in latency and a 14.67% reduction in energy consumption. Using existing NoC tools, the energy-latency product of SNN architectures is, on average, 82.71% lower than that of the baseline architectures.

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Section: Introductionmentioning

confidence: 99%

Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks

Islam,

Majurski,

Kwon

et al. 2024

Sensors

Self Cite

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“…The relative power consumed per nm 2 increases exponentially as the technology scales down. This higher power led designers to constantly come up with innovative techniques to reduce the power while trying to meet all the design constraints that impact the performance [8,20,23,25,28,31,41,48,52].…”

Section: Introductionmentioning

confidence: 99%

Design Automation of Series Resonance Clocking in 14-nm FinFETs

Challagundla,

Bezzam,

Islam

2023

Circuits Syst Signal Process

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Power-performance constraints have been the key driving force that motivated the microprocessor industry to bring unique design techniques in the past two decades. The rising demand for high-performance microprocessors increases the circuit complexity and data transfer rate, resulting in higher power consumption. This work proposes a set of energy recycling resonant pulsed flip-flops to reuse some of the dissipated energy using series inductor-capacitor (LC) resonance. Moreover, this work also presents wideband clocking architectures that use series LC resonance and an inductor tuning technique. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor tuning technique aids in reducing the skew, increasing the robustness of the clock networks. This new resonant clocking architecture saves over 43% power and 90% reduced skew in clock tree networks and saves 44% power and 90% reduced skew in clock mesh networks, clocking a range of 1-5 GHz frequency, compared to conventional primary-secondary flip-flop-based clock networks. Implementation of resonant clock architectures on standard clock network benchmarks depicts 66% power Dhandeep Challagundla

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“…A significant portion of dynamic power consumed in a highfrequency design is due to the switching activity in the clock network [10]. To address this, several low power techniques such as dynamic voltage and frequency scaling (DVFS) [11], clock gating [12] and LC resonant clocking [13]- [17], currentmode clocking [18]- [20] are commonly used. Among them, inductor-based LC resonant clocking techniques have great potential to save switching power due to their constant phase and magnitude.…”

Section: Introductionmentioning

confidence: 99%

Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks

Challagundla¹,

Mehedi²,

Bezzam³

et al. 2022

Preprint

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As the demand for high-performance microprocessors increases, the circuit complexity and the rate of data transfer increases resulting in higher power consumption. We propose a clocking architecture that uses a series LC resonance and inductor matching technique to address this bottleneck. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor matching technique aids in reducing the skew, increasing the robustness of the clock network. This new resonant architecture saves over 43% power and 91% skew clocking a range of 1-5 GHz, compared to a conventional primary-secondary flip-flop-based CMOS architecture.

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Differential current-mode clock distribution

Cited by 8 publications

References 12 publications

Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks

Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks

Design Automation of Series Resonance Clocking in 14-nm FinFETs

Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks

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