Although we may be at the end of Moore's law, lowering chip power consumption is still the primary driving force for the designers. To enable low-power operation, we propose a resonant energy recovery static random access memory (SRAM). We propose the first series resonance scheme to reduce the dynamic power consumption of the SRAM operation. Besides, we identified the requirement of supply boosting of the write buffers for proper resonant operation. We evaluated the resonant 144KB SRAM cache through SPICE and test chip using a commercial 28nm CMOS technology. The experimental results show that the resonant SRAM can save up to 30% dynamic power at 1GHz operating frequency compared to the state-of-the-art design.
An energy efficient and area sav scheme using new resonant techniques is illust of 1024 flip-flops. Energy recovering pulse clocking is designed to drive explicit-pulsed n latches. A pre-driver that generates trackin transition of clock for dual edge (DET) op across PVT. While both the pre-driver and dr for energy reduction and recycling, the indu enough to fit over the active circuitry resulti and active area reductions. The pulsed resonan needs only 1/10 th the inductance of conventi circuits. Monte Carlo simulations using 4 interconnect models show that the design s Voltage and Frequency Scaling from 200MHz@0.5V.
As the demand for high-performance microprocessors increases, the circuit complexity and the rate of data transfer increases resulting in higher power consumption. We propose a clocking architecture that uses a series LC resonance and inductor matching technique to address this bottleneck. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor matching technique aids in reducing the skew, increasing the robustness of the clock network. This new resonant architecture saves over 43% power and 91% skew clocking a range of 1-5 GHz, compared to a conventional primary-secondary flip-flop-based CMOS architecture.
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