Different configurations for dynamic latched comparators used in ultra low power Analog to Digital converters

Abozeid, Karim M.; Aboudina, Mohamed M.; Khalil, A. H.

doi:10.1109/icengtechnol.2014.7016771

Cited by 3 publications

(4 citation statements)

References 4 publications

(7 reference statements)

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“…To reduce the power consumption, there are many diferent methods, as will be demonstrated in this paper. Various confgurations for the comparator [14][15][16][17][18][19][20][21][22][23][24] can be used to reduce power consumption, time delay, and noise efects. In addition, the modifed binary-weighted CDAC structure can save area and energy.…”

Section: Sar Adc Architecturementioning

confidence: 99%

“…Te methodology for implementing the SAR comparator targets the lowering of power consumption to be convenient for biomedical applications. Likewise, several performance factors are considered besides the consumed power, such as accuracy, speed, resolution, propagation time delay, input-referred ofset voltage, supply sensitivity, and meta-stability [14].…”

Section: Different Configuration Of Dynamic Comparatormentioning

confidence: 99%

“…In the two-stage comparator design, a preamplifer stage with a single-stage dynamic latch is connected in a cascaded scheme as shown in Besides the amplifcation of the input signal, this comparator scheme prevents the kick-back noise, reduces the input-referred ofset voltage, and improves the comparison speed [14].…”

Section: Two-stage Dynamic Latchmentioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Section: Sar Adc Architecturementioning

confidence: 99%

Section: Different Configuration Of Dynamic Comparatormentioning

confidence: 99%

See 1 more Smart Citation

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

View full text Add to dashboard Cite

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“…Furthermore, the R-latch and SR-latch realized using VCVS 3 with gain A L and the latch mode time constant τ L = R L •C L and Verilog-A based analog latch and limiter. In this case, A L and τ L determines the positive feedback operation of the R-latch [21], where although R ic and C ic do not directly affect the performance of VCVS 3 , the R oc and C oc , which are equivalent to the input impedance of the R-latch, determine the preamp. bandwidth.…”

Section: Comparator Macro Modelmentioning

confidence: 99%

Macro Model for Discrete-Time Sigma‒Delta Modulators

Lee

2022

Electronics

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This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.

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