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1998
DOI: 10.1016/s0026-2714(97)00206-0
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Dielectric Reliability Measurement Methods: A Review

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Cited by 101 publications
(31 citation statements)
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“…Recently a detailed review was given by Martin et al 10 In the most straightforward way, the time to breakdown can be measured in an experiment in which a constant bias voltage ͑or current͒ is applied to the junction. This method has the disadvantage of the a priori unknown time to breakdown, which can exceed several days when measuring at low stress voltages, making these measurements less convenient.…”
Section: Resultsmentioning
confidence: 99%
“…Recently a detailed review was given by Martin et al 10 In the most straightforward way, the time to breakdown can be measured in an experiment in which a constant bias voltage ͑or current͒ is applied to the junction. This method has the disadvantage of the a priori unknown time to breakdown, which can exceed several days when measuring at low stress voltages, making these measurements less convenient.…”
Section: Resultsmentioning
confidence: 99%
“…HfO 2 , $25) are investigated widely for their potential use as dielectric layers in advanced metal-oxide-semiconductor (MOS) devices [1,2] aiming to the substantial reduction of gate leakage currents [3]. An important consequence will be the use of thicker (higher permittivity) dielectric layers, and one would also expect to reduce the stress-induced leakage current and improve the reliability of the corresponding devices [4]. During the past decade, germanium (Ge) based MOS devices are extensively studied due to its high mobility [1,2] for the future semiconductor and integrated circuits industry.…”
Section: Introductionmentioning
confidence: 99%
“…A methodology to study the BD reversibility has been developed ( Figure 1). Current Limited -Ramped Voltage Stresses (CL-RVS) were applied to the gate to provoke the dielectric BD, followed by a Stepped Ramp Voltage Stress (S-RVS) [10] without current limitation, to recover the dielectric, following an iterative sequence, as shown in Figure 1. During the S-RVS the gate voltage is increased in aprox.…”
Section: Iisamples and Experimental Proceduresmentioning
confidence: 99%