Dielectric based antifuse for logic and memory ICs

Hamdy, E.; McCollum, J.; Chen, S.-O.; Chiang, Su‐Yu; Eltoukhy, S.; Chang, Jung Min; Speers, T.; Mohsen, A.M.

doi:10.1109/iedm.1988.32929

Cited by 71 publications

(23 citation statements)

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“…Conventionally, most of the OTP is fabricated using either special process which requires additional masks in addition to the standard CMOS process available form common foundries [1]. Some high density OTP structures are not CMOS compatible in order to achieve very compact structure [2].…”

Section: Introductionmentioning

confidence: 99%

Diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process

Lee

Kwong

et al. 2009

2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)

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Section: Introductionmentioning

confidence: 99%

Diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process

Lee

Kwong

et al. 2009

2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)

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“…They can be an oxide-nitride-oxide (ONO) layer sandwiched between diffusion and polysilicon [16], or between two layers of polysilicon [17], or a metal-insulator-metal (MIM) stack [18], or gate oxide itself [19]. These technologies are typical of low-density and slow programming.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of<tex>$hboxSiO_2$</tex>Antifuse in a 3D-OTP Memory

Yang

Meeks

et al. 2004

IEEE Trans. Device Mater. Relib.

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We have evaluated an antifuse technology used in a novel three-dimensional one-time-programmable (3D-OTP) nonvolatile solid-state memory. The 3D-OTP memory uses deposited polysilicon antifuse sandwiches to build its memory cells. The polysilicon based SiO 2 antifuse show different breakdown characteristics compared to conventional traditional gate oxides. Long-term storage tests show that this 3D-OTP solid-state memory not only can be a general purpose ROM, but also can be an ideal media for archiving.Index Terms-Antifuse, archival media, nonvolatile memory, oxide breakdown, 3D memory.

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“…Two approaches have been used to implement anti-fuses. Dielectric anti-fuses are composed of an oxide-nitride-oxide dielectric positioned between N+ diffusion and polysilicon [93]. The application of a high voltage causes the dielectric to break down and form a conductive link with a resistance of typically between 100 and 600 ohms [55,90].…”

Section: Anti-fuse Programming Technologymentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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Dielectric based antifuse for logic and memory ICs

Cited by 71 publications

References 1 publication

Diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process

Diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process

Evaluation of<tex>$hboxSiO_2$</tex>Antifuse in a 3D-OTP Memory

FPGA Architecture: Survey and Challenges

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Dielectric based antifuse for logic and memory ICs

Cited by 71 publications

References 1 publication

Diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process

Diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process

Evaluation of&lt;tex&gt;$hboxSiO_2$&lt;/tex&gt;Antifuse in a 3D-OTP Memory

FPGA Architecture: Survey and Challenges

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Evaluation of<tex>$hboxSiO_2$</tex>Antifuse in a 3D-OTP Memory