Die to Wafer Hybrid Bonding and Fine Pitch Considerations

Workman, Thomas; Mirkarimi, Laura; Theil, Jeremy A.; Fountain, G. G.; Bang, KM; Lee, Bongsub; Uzoh, Cyprian; Suwito, Dominik; Gao, Guanghai; Mrozek, P.

doi:10.1109/ectc32696.2021.00326

Cited by 18 publications

(1 citation statement)

References 6 publications

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“…In both integration schemes, distortion along the bond interface is critical for device performance. Distortion (or misalignment) in hybrid bonding can directly degrade electrical performance [1], whereas distortion residuals contribute to overlay error in subsequent pattern layers. Therefore, it is important to study the wafer bonding process in order to control and optimize bond process related distortion.…”

Section: Introductionmentioning

confidence: 99%

Overlay performance in permanent bonded wafer integration schemes

Belyansky

Netzband

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.

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Section: Introductionmentioning

confidence: 99%