Die Embedding Challenges for EMIB Advanced Packaging Technology

Duan, Guijiang; Kanaoka, Yosuke; McRee, Robin; Nie, Bai; Manepalli, Rahul

doi:10.1109/ectc32696.2021.00012

Cited by 42 publications

(13 citation statements)

References 3 publications

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“…Embedded multi-interconnect bridge (EMIB) technology is an advanced, cost-effective approach to deliver localized high density on-package interconnects for individually optimized links between heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths among multiple dice in the same package. [13][14][15][16][17] EMIB allows a significant level of design flexibility in the placement of heterogeneous dice and mixing of components to optimize system level performance. It is compatible with different Si technology nodes and enables large form factor (FF) die stitching capability with a high number of bridges embedded in the package substrate.…”

Section: Introductionmentioning

confidence: 99%

EMIB and advanced substrate packaging technologies to enable heterogeneous integration (HI) applications

Duan,

Mahajan,

Manepalli

et al. 2024

Jpn. J. Appl. Phys.

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Heterogeneous chiplet integration has become a crucial performance enabler in the microelectronics industry by providing the flexibility of die disaggregation, and the ability to mix/match different IP blocks optimized on different Si nodes in a single package. It shows great potential in supercomputing, autonomous driving, artificial intelligence, and machine learning applications. With rising demand in high performance computing (HPC), the key focus in Heterogeneous Integration (HI) scaling has been to push interconnect density with increased bandwidth and improved power efficiency. In this paper, we provide an overview of Embedded Multi-Interconnect Bridge (EMIB) pack-aging technology scaling and discuss key considerations for advanced substrate packaging technologies to enable further HI applications.

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Section: Introductionmentioning

confidence: 99%

EMIB and advanced substrate packaging technologies to enable heterogeneous integration (HI) applications

Duan,

Mahajan,

Manepalli

et al. 2024

Jpn. J. Appl. Phys.

Self Cite

View full text Add to dashboard Cite

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“…The Si-bridge allowed for finer CDs, becoming what is known as 2.5D packaging. [3][4][5] As the demand for die-to-die communication speed increased, the dies were stacked vertically and connected with TSVs. The vertically stacked die connected with TSVs became the 3D package.…”

Section: Introductionmentioning

confidence: 99%

Minimizing die fracture in 3DIC die integration

Bravo,

Morey-Chaisemartin,

Beisser

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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Background: The demand for high-performance semiconductor products has led to reduced wafer feature size, lowered package size, and an ever-thinner die for advanced three-dimensional (3D) packaging. Dies down to a thickness of 5 μm have been demonstrated. One significant barrier is the fragility of the thin dies, their overall thin form factor, and their impact on yield, reliability, and costs.Aim: We explore the current state of the art in the current crack stop and outline the shortcomings moving forward for stacked 3D integrated circuits (3DIC).Approach: Using a theoretical understanding of fracture mechanics and the new biomimetic concept adapted from nature, we show the implementation of the new crack stop insertions in the die frame for a next-generation 3DIC product. Results:The proposed crack stop can be easily inserted in the die frame with electronic design automation (EDA) tools using a Python interpreter and has the capability to arrest a crack near its initiation point. Conclusions:We show the feasibility of the implementation through EDA tools and outline the next step.

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“…One example is embedding Si fine line interposer on conventional package substrates. 4 Another is using Si or glass as a carrier and form a fine wiring interposer. 5 Also in the lithography equipment, various methods have been proposed, such as direct imaging, 6 stitching, and panellevel stepper.…”

Section: Introductionmentioning

confidence: 99%

Development of panel-level organic lithography equipment for advanced packaging

Sohara,

Abe,

Yamauchi

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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Background: Heterogeneous integration has been used to enhance functionality and improve operation performance by integrating separately manufactured components into system in package. To realize this high density and high performance system, continuous miniaturization is required for Cu interconnect wiring on an organic substrate.Aim: The aim is to clarify the lithography issues for 5 μm L/S Cu wiring formation in the next generation. Lithographic performances, such as resolution, depth of focus (DOF), and overlay accuracy, are evaluated on an organic substrate, and the improvement of lithographic process margin is also investigated. Here, the exposure field of stepper is wide, that is, 62500 mm 2 .Approach: The DOF is calculated and evaluated based on the negative dry film resist with thickness of 15 μm. Overlay accuracy was measured, using a multipoint alignment procedure. Result and Conclusion:First result is patterning. For realizing 5 μm L/S Cu wiring in semi-additive process, resist patterning of 3.5/6.5 or 3∕7 μm L/S is required due to seed Cu layer etching. Under two projection optics conditions (lens C: 5 μm L/S resolution and lens D: 3 μm L/S resolution), the process margin values of 3.5/6.5 and 3∕7 μm L/S were evaluated. It was found that the process margin of 3.5∕6.5 μm L/S is AE40 μm (lens C)/ AE30 μm (lens D), and the process margin of 3∕7 μm L/S is AE10 μm (lens C) AE20 μm (lens D). These process margin values are enough for 5 μm L/S Cu wiring formation. And the second result is overlay. The overlay of the lithography equipment is 1.0 μm or less for deformed substrates while maintaining productivity by simultaneous multipoint measurement.

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Die Embedding Challenges for EMIB Advanced Packaging Technology

Cited by 42 publications

References 3 publications

EMIB and advanced substrate packaging technologies to enable heterogeneous integration (HI) applications

EMIB and advanced substrate packaging technologies to enable heterogeneous integration (HI) applications

Minimizing die fracture in 3DIC die integration

Development of panel-level organic lithography equipment for advanced packaging

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