2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 2016
DOI: 10.1109/micro.2016.7783704
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Dictionary sharing: An efficient cache compression scheme for compressed caches

Abstract: The effectiveness of a compressed cache depends on three features: i) the compression scheme, ii) the compaction scheme, and iii) the cache layout of the compressed cache. Skewed compressed cache (SCC) and yet another compressed cache (YACC) are two recently proposed compressed cache layouts that feature minimal storage and latency overheads, while achieving comparable performance over more complex compressed cache layouts. Both SCC and YACC use compression techniques to compress individual cache blocks, and t… Show more

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Cited by 25 publications
(29 citation statements)
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References 27 publications
(27 reference statements)
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“…3.1). As previously discussed, we choose VSC because it is the most commonly used in cache compression work [8,9,17,41,42,60,70,81]. There are two differences between VSC and our simple example.…”
Section: Pack+probe Implementation On Vscmentioning
confidence: 99%
See 1 more Smart Citation
“…3.1). As previously discussed, we choose VSC because it is the most commonly used in cache compression work [8,9,17,41,42,60,70,81]. There are two differences between VSC and our simple example.…”
Section: Pack+probe Implementation On Vscmentioning
confidence: 99%
“…In this paper, we provide an answer in the affirmative by analyzing the security of memory hierarchy compression, specifically cache compression. Compression is an attractive technique to improve memory performance, and has received intense development from both academia [3,4,8,9,37,40,55,59,60,62,69,70,81,90,92] and industry [17,18,31,41,45,61]. Several deployed systems already use memory-hierarchy compression.…”
Section: Introductionmentioning
confidence: 99%
“…Compression exploits redundancy in data values to increase effective capacity of a given substrate. Prior work has looked at compression for improving the capacity of SRAM caches [4,28,34,35]. As decompression latency is in the critical path of cache access, these proposals use simple compression schemes such as Frequent Pattern Compression (FPC) [5], Base-Delta-Immediate (BDI) [31], CPACK [11], and ZCA [17], that can perform decompression within a minimal number of cycles.…”
Section: Compressing On-chip Sram Cachesmentioning
confidence: 99%
“…Therefore, LCP can utilize compression not only for capacity but also for bandwidth benefits. Unfortunately, the page mapping and organization of LCP must be done using the OS, as the OS is required to know the compressed page size, in order to access the adjusted 1 Recent studies on SRAM cache compression propose sharing tags between a larger number of sets (say 4x sets, called superblocks) to reduce tag and metadata overhead [28,34,35]. However, when applied on DRAM caches, these designs increase the number of sets that must be checked on each access, which can waste bandwidth.…”
Section: Compressing Main Memorymentioning
confidence: 99%
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