Safecracker: Leaking Secrets through Compressed Caches

Tsai, Po-An; Sánchez, Andrés; Fletcher, Christopher W.; Sánchez, Daniel

doi:10.1145/3373376.3378453

Cited by 12 publications

(3 citation statements)

References 76 publications

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“…on common compressed cache architecture, VSC [97] that uses Based-Delta Immediate compression [98] algorithm was performed in [99] to leak secret information. Formal checking of new cache vulnerability before manufacturing the cache is another promising future line of work.…”

Section: % (Parsec)mentioning

confidence: 99%

A Survey on Cache Timing Channel Attacks for Multicore Processors

Kaur

Das

2021

J Hardw Syst Secur

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Cache timing channel attacks has attained a lot of attention in the last decade. These attacks exploits the timing channel created by the significant time gap between cache and main memory accesses. It has been successfully implemented to leak the secret key of various cryptography algorithms. The latest advancements in cache attacks also exploit other microarchitectural components such as hardware prefetchers, branch predictor, and replacement engine, in addition to the cache memory. Detection of these attacks is a difficult task as the attacker process running in the processor must be detected before significant portion of the attack is complete. The major challenge for mitigation and defense mechanisms against these attacks is maintaining the system performance while disabling or avoiding these attacks. The overhead caused by detection, mitigation and defense mechanism must not be significant to system's performance. This paper discusses the research carried out in three aspects of cache security: cache timing channel attacks, detection techniques of these attacks, and defense mechanisms in details. KeywordsCache security • Cache timing channel attack • Side-channel attack • Covert channel attack • Detection techniques • Defense mechanisms

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Section: % (Parsec)mentioning

confidence: 99%

A Survey on Cache Timing Channel Attacks for Multicore Processors

Kaur

Das

2021

J Hardw Syst Secur

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“…In the context of hardware data compression, Tsai et al [91] have applied this exploit to BDI [69]. Assuming that an attacker controls the contents of a line, except for the x-bit secret it wants to unveil, their proposal combines brute force with exploration space reduction.…”

Section: Interactions With Securitymentioning

confidence: 99%

Understanding Cache Compression

Carvalho

Seznec

2021

ACM Trans. Archit. Code Optim.

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Hardware cache compression derives from software-compression research; yet, its implementation is not a straightforward translation, since it must abide by multiple restrictions to comply with area, power, and latency constraints. This study sheds light on the challenges of adopting compression in cache design—from the shrinking of the data until its physical placement. The goal of this article is not to summarize proposals but to put in evidence the solutions they employ to handle those challenges. An in-depth description of the main characteristics of multiple methods is provided, as well as criteria that can be used as a basis for the assessment of such schemes. It is expected that this article will ease the understanding of decisions to be taken for the design of compressed systems and provide directions for future work.

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“…Tsai et al [55] demonstrated cache timing attacks on compressed caches, which can leak a secret key in under 10 ms.…”

Section: B Prior Data Compression Attacksmentioning

confidence: 99%