Diamond MOSFETs using 2D hole gas with 1700V breakdown voltage

Kawarada, Hiroshi; Yamada, Tetsuya; Xu, Dehong; Kitabayashi, Y.; Shibata, Masanobu; Matsumura, Daiju; Kobayashi, M.; Saito, Toshiki; Kudo, Tetsuichi; Inaba, Masafumi; Hiraiwa, Atsushi

doi:10.1109/ispsd.2016.7520883

Cited by 30 publications

(25 citation statements)

References 17 publications

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“…In this work, the 25-nm-thick ALD-grown Al 2 O 3 layer was used as both a gate insulator and a passivation layer. As reported by Daicho et al [16] and Kawarada et al [21], during grown Al 2 O 3 using ALD with water as oxidants, a fresh 2DHG layer produces on the C-H diamond and Al 2 O 3 interface. This conductive layer is protected by the Al 2 O 3 dielectric layer, which lead to the improvement of the stability of the 2DHG.…”

Section: Resultsmentioning

confidence: 61%

Low On-Resistance H-Diamond MOSFETs With 300 °C ALD-Al₂O₃Gate Dielectric

Ren

et al. 2020

IEEE Access

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C-H diamond metal-oxide-semiconductor field effect transistors with different structures were fabricated on the same polycrystalline diamond plate. Devices A and B with 25-nm-thick high temperature (300 • C) atomic layer deposition grown Al 2 O 3 dielectric have the same source-to-drain distance of 6 µm and different gate length of 2 µm and 6 µm, respectively. Both devices show ultra-high on/off ratio of over 10 10 and ultra-low gate leakage of below 10 −10 A and continuous measurement stability. Device B with the source/drain-channel interspaces eliminated has achieved an on resistance of 46.20 •mm, which is record low in the reported 6-µm H-diamond MOSFETs with the gate dielectric prepared at high temperature (≥ 300 • C). Meanwhile, device B shows larger drain current in a large portion of the linear region at V GS = −6 V, and a just slightly smaller I Dmax compared with device A though its L G is three times of that of device A. A simple model of I D was used to explain the physics behind this phenomenon. In addition, the breakdown voltage is 145 V for device A and 27 V for device B, corresponding to the average breakdown field of about 0.72 MV/cm and 10.8 MV/cm, respectively.

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Section: Resultsmentioning

confidence: 61%

Low On-Resistance H-Diamond MOSFETs With 300 °C ALD-Al₂O₃Gate Dielectric

Ren

et al. 2020

IEEE Access

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“…The shift in threshold voltage (extracted at Id = 0.1 mA/mm and Vds = -10 V) from 0.45 to 1.7 V and increase in intrinsic transconductance from 287 to 325 mS/mm (extracted utilizing equation (2)) also strongly suggest modification to the intrinsic gate contact, most likely resulting from the 400°C anneal. Although a model to describe the formation of the 2D hole channel at the H-diamond/Al2O3 interface has recently been proposed for ALD-deposited Al2O3 [18], this mechanism may not apply to electron-beam evaporated Al2O3 as used in this work. The role of potential residual atmospheric adsorbates between the diamond and Al2O3 may also play an important role in these devices and warrants further investigation.…”

Section: Discussionmentioning

confidence: 99%

Performance Enhancement of Al₂O₃/H-Diamond MOSFETs Utilizing Vacuum Annealing and V₂O₅ as a Surface Electron Acceptor

Macdonald

Crawford

Tallaire

et al. 2018

IEEE Electron Device Lett.

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We report on the performance enhancement of 250 nm gate-length H-diamond FETs through thermal treatment of devices at 400°C and the incorporation of V2O5 as a surface electron acceptor layer. Encapsulation of the H-diamond surface with V2O5 is found to increase the transfer doping efficiency and reduce device access resistance. A reduction in ohmic contact resistance and channel resistance beneath the gate after thermal treatment at 400°C was found to further reduce device onresistance and increase the maximum drain current and peak transconductance. These devices demonstrate the highest drain current (375 mA/mm) and transconductance (98 mS/mm) yet reported for H-diamond FETs of this gate length that incorporate an electron acceptor oxide layer.

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“…Firstly, we defined a simplified 2D unit cell as already done for the normally-on JFET, neglecting in this way some of the 3D effects which occur in the real device (see figure 2). The breakdown voltage target has been arbitrarily chosen to be 2 kV which is a value comparable with the state-of-the-art breakdown voltage of other diamond FETs [6,16,55]. Then, we defined the input parameters which are the gate doping (n-doping), the gate-to-source distance (L'(s-g)) and the gate width (WN).…”

Section: Design Technique For a Normally-off Jfetmentioning

confidence: 99%

“…Regarding the power electronics applications of diamond, the high activation energy of n-type dopants (0.57 eV for phosphorus) has hindered the fabrication of bipolar devices such as BJTs (Bipolar Junction Transistors) and IGBTs (Insulated Gate Bipolar Transistors) due to the high resistivity of the n-layers and the large turn-on junction voltages. For this reason, the research on diamond FETs (Field Effect Transistors) devices has been essentially focused on unipolar p-type devices, especially delta-doped FETs, HFETs (Hydrogen terminated FETs) and p-type JFETs (Junction FETs) [14][15][16][17][18][19]. However, the large leakage current observed in delta-doped structures [19] and the lack of the mobility enhancement in such devices have limited the performance and applications of delta-doped diamond FETs.…”

Section: Introductionmentioning

confidence: 99%

Design of a normally-off diamond JFET for high power integrated applications

Donato

Pagnano

Napoli³

et al. 2017

Diamond and Related Materials

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Normally-on (depletion mode) and normally-off (enhancement mode) diamond Junction Field Effect Transistors (JFETs) have been analyzed by means of a commercially available TCAD software. First, the parameters used for describing the incomplete ionization, avalanche, and mobility models in diamond have been discussed and assessed against the state-of-the-art. The on- and off-state electrical characteristics of diamond JFETs have been simulated with the suggested parameter values and matched with a set of available experimental data. Secondly, an optimization technique which can improve the performance of an enhancement mode diamond JFET that operates in the unipolar conduction regime has been proposed. This method takes into account the unique properties and limitations of diamond and highlights the main issues that can arise from the design of a normally-off diamond JFET. In particular, the crucial effect of the high temperature on the performance of the normally-off JFET has been investigated. The adopted technique is mainly based on a design of TCAD experiments and no mathematical algorithms have been developed for the calculation of the optimized set of parameters

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Diamond MOSFETs using 2D hole gas with 1700V breakdown voltage

Cited by 30 publications

References 17 publications

Low On-Resistance H-Diamond MOSFETs With 300 °C ALD-Al₂O₃Gate Dielectric

Low On-Resistance H-Diamond MOSFETs With 300 °C ALD-Al₂O₃Gate Dielectric

Performance Enhancement of Al₂O₃/H-Diamond MOSFETs Utilizing Vacuum Annealing and V₂O₅ as a Surface Electron Acceptor

Design of a normally-off diamond JFET for high power integrated applications

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Diamond MOSFETs using 2D hole gas with 1700V breakdown voltage

Cited by 30 publications

References 17 publications

Low On-Resistance H-Diamond MOSFETs With 300 °C ALD-Al2O3Gate Dielectric

Low On-Resistance H-Diamond MOSFETs With 300 °C ALD-Al2O3Gate Dielectric

Performance Enhancement of Al2O3/H-Diamond MOSFETs Utilizing Vacuum Annealing and V2O5 as a Surface Electron Acceptor

Design of a normally-off diamond JFET for high power integrated applications

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Low On-Resistance H-Diamond MOSFETs With 300 °C ALD-Al₂O₃Gate Dielectric

Low On-Resistance H-Diamond MOSFETs With 300 °C ALD-Al₂O₃Gate Dielectric

Performance Enhancement of Al₂O₃/H-Diamond MOSFETs Utilizing Vacuum Annealing and V₂O₅ as a Surface Electron Acceptor