Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree

Abstract

If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.

Scan Based Silicon Debug

“…As described in [11], TSMC found a few die suffered from compound hold-time violation, where hold-time errors happened both on scan chains and system logic. The design has 45M gates that were manufactured with 28nm technology.…”