di/dt Noise in CMOS Integrated Circuits

Distributed power network co-design with on-chip power supplies and decoupling capacitors

“…A 20 x 20 power grid with five decoupling capacitors placed at N (3,3) , N (3,17) , N (10,10) , N (17, 3) , and N (17,17) and four on-chip power supplies located at N (3,10) , N (10,3) , N (10,17) , and N (16,10) is evaluated. For rise and fall times of the load current of 50 ps and 150 ps, respectively, the effective region for the decoupling capacitors and power supplies is illustrated in Fig.…”

“…Faster transition times and higher current demands produce larger voltage droop due to resistive IR and inductive L di/dt noise [3]. Due to the self-and mutual inductance of the power lines, the power grid impedance increases with frequency [1].…”

Analyzing internal-switching induced simultaneous switching noise

“…The equivalent lumped-model circuit is drawn in Figure 3, where all elements are represented by their complex-frequency domain models [8]. Using the loop current law, the ground and power bounces are expressed as is V DD for t ≥ 0, Equations (1) and (2) imply the symmetric bounce signal on the power rail and ground rail, and the phase difference between them is 180° [9]. It's obvious that when SSN due to internal gate switching is considered, the signal bounce on the power rail is as significant as that on the ground rail, and both the power-rail and groundrail pin impedances contribute to these voltage surges.…”

“…The working frequency is then found numerically by U in Equation (9). The analytical solution of V n can be found.…”

“…[9] suggested C decp should be 5 times larger than C sw if the gate activity ratio is 1. Due to the presence of C decp , the driving nMOS may exit saturation region when the first peak of SSN comes.…”