DFX of a 3&lt;sup&gt;rd&lt;/sup&gt; Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor

Parulkar, Ishwar; Anandakumar, S.; Agarwal, Gaurav; Liu, G.; Rajan, K.; Chiu, F.; Pendurkar, R.

doi:10.1109/test.2008.4700552

Cited by 10 publications

(9 citation statements)

References 16 publications

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“…Trace buffers [15], [16] and the freezing or dump technique [17]- [20] used in silicon debug are useful for localizing a board-level functional failure. However, trace buffers can provide real-time observation for only a few signals across a limited number of clock cycles.…”

Section: Introductionmentioning

confidence: 99%

Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster–Shafer Theory

Fang

Chakrabarty

Wang

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Despite recent advances in structural test methods, the diagnosis of the root cause of board-level failures for functional tests remains a major challenge. A promising approach to address this problem is to carry out fault diagnosis in two phases-suspect faulty components on the board or modules within components (together referred to as blocks in this paper) are first identified and ranked, and then fine-grained diagnosis is used to target the suspect blocks in a ranked order. We propose a new method based on dataflow analysis and DempsterShafer (DS) theory for ranking faulty blocks in the first phase of diagnosis. The proposed approach transforms the information derived from one functional test failure into multiple-stage failures by partitioning the given functional test into multiple stages. A measure of "belief" is then assigned to each block based on the knowledge of each failing stage, and the DS theory is subsequently used to aggregate the beliefs from multiple failing stages. Blocks with higher beliefs are ranked on the top of the candidate list. Simulations on an industry design for a network interface application as well as on an open source system-ona-chip show that the proposed method can provide accurate ranking for most board-level functional failures. Index Terms-Board-level, dataflow analysis, Dempster-Shafer (DS) theory, diagnosis, functional failure.

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Section: Introductionmentioning

confidence: 99%

Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster–Shafer Theory

Fang

Chakrabarty

Wang

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…On the other side, multicore processor like the Cell processor [14] , the Niagra2 processor [15] , and the UltraSPARC CMT processor [16] use the dedicated scan inputs and outputs for each core. This approach enables the diagnosis and determination of defective cores easier but leads to more test time since the length of scan chains is much longer.…”

Section: Introductionmentioning

confidence: 99%

Design for Testability Features of Godson-3 Multicore Microprocessor

Liu

et al. 2011

J. Comput. Sci. Technol.

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This paper describes the design for testability (DFT) challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar (SMOC) on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism (TAM) is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

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“…The trace buffer technique [11] [12] and freezing/dump technique [13] [14] [15] [16] used in silicon debug are useful for localizing a board-level functional failure. Trace buffers are commonly used to capture and observe data from signals during insystem silicon debug.…”

Section: Introductionmentioning

confidence: 99%

“…However, this method is only effective for synchronous designs and it is not applicable to multiple clock domains driven by different PLLs, which is common in modern boards and systems. The freezing/dump feature is also implemented in Sun's microprocessors [14] [15] [16]. A custom clock controller allows the chip's internal clock to be disabled in any desired cycle during normal functional operation.…”

Section: Introductionmentioning

confidence: 99%

Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures

Fang

Wang

et al. 2010

2010 19th IEEE Asian Test Symposium

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A common scenario in industry today is "No Trouble Found" (NTF) due to functional failures. A component on a board fails during board-level functional test, but it passes the Automatic Test Equipment (ATE) test when it is returned to the supplier for warranty replacement or service repair. To find the root cause of NTF, we define an innovative deterministic test, namely functional scan test. We also propose two approaches for using functional scan test to adequately mimic functional state space. The first approach allows us to select a given number of initial states in linear time and functional scan tests resulting from these selected states are used to mimic the functional state space effectively. The second approach adopts a state-injection technique. Experiments on an industry design show that by using either multiple initial states or state injection, functional scan test with appropriate functional constraints can mimic the functional state space well, measured by appropriate coverage metrics. Therefore, it is feasible to use functional scan test to detect board-level functional failures in a controlled deterministic environment and diagnose the root cause to faulty wires/gates inside a component. It is also shown that the proposed method outperforms a random method in selecting the given number of effective initial states.

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DFX of a 3<sup>rd</sup> Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor

Cited by 10 publications

References 16 publications

Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster–Shafer Theory

Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster–Shafer Theory

Design for Testability Features of Godson-3 Multicore Microprocessor

Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures

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