DFSB-Based Thermal Management Scheme for 3-D NoC-Bus Architectures

Zheng, Jing-Hua; Wu, Ning; Zhou, Lei; Ye, Yunfei; Sun, Ke

doi:10.1109/tvlsi.2015.2439698

Cited by 11 publications

(5 citation statements)

References 36 publications

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“…Several works have used trace-based evaluation for core thermal management policies [16,17,34,60]. Cox et al [16] use trace-based HotSpot simulation to obtain temperature and perform a thermal-aware mapping of streaming applications on 3D processors.…”

Section: Background and Related Workmentioning

confidence: 99%

CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems

Siddhu¹,

Kedia²,

Pandey³

et al. 2021

Preprint

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Processing cores and the accompanying main memory working in tandem enable the modern processors. Dissipating heat produced from computation remains a significant problem for processors. Therefore, the thermal management of processors continues to be an active subject of research. Most thermal management research takes place using simulations, given the challenges involved in measuring temperatures in real processors. Fast yet accurate interval thermal simulation toolchains remain the research tool of choice to study thermal management in processors at system-level. However, since in most existing processors, core and memory are fabricated on separate packages, with the memory having lower power densities than the cores, thermal management research in processors primarily focused on the cores. Consequently, state-of-the-art interval thermal simulation toolchains remain limited to core-only simulations.The memory bandwidth limitations associated with 2D processors lead to high-density 2.5D and 3D packaging technology. 2.5D packaging technology places cores and memory on the same package. 3D packaging technology takes it further by stacking layers of memory on the top of cores themselves. These new packagings significantly increase the power density of the processors, making them prone to overheating. Therefore, mitigating thermal issues in high-density processors (packaged with stacked memory) becomes an even more pressing problem. However, given the lack of thermal modeling for memories in existing interval thermal simulation toolchains, they are unsuitable for studying thermal management for high-density processors.To address this issue, we present CoMeT , the first integrated Core and Memory interval Thermal simulation toolchain. CoMeT comprehensively supports thermal simulation of high-and low-density processors corresponding to four different core-memory (integration) configurations -off-chip DDR memory, off-chip 3D memory, 2.5D, and 3D. CoMeT supports several novel features that facilitate overlying system research. Compared to an equivalent state-of-the-art core-only toolchain, CoMeT adds only an additional ∼5% simulation-time overhead. The source code of CoMeT has been made open for public use under the MIT license.

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Section: Background and Related Workmentioning

confidence: 99%

CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems

Siddhu¹,

Kedia²,

Pandey³

et al. 2021

Preprint

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“…However, compression ratio using this technique is very low. In [22], a 3-D NoC-bus hybrid architecture presented to make routing more efficient in bus architectures of VLSI design through 3-D IC technology hence the power consumption and this system also reduces the computational cost. However, due to high interconnect traffic the thermal issues can degrade performance of the system.…”

Section: Related Workmentioning

confidence: 99%

Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters

Murthy¹,

Sridhar²

2018

IJEECS

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<p>In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and power distribution to multi-core architectures is also posing a challenge to power distribution networks in the integrated circuits. Clock distribution networks for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. Therefore, this paper introduce low swing signaling schemes to decrease delay and power consumption. A comparative study presented of low voltage signaling schemes in terms of delay, power consumption and power delay product. Here, we have presented a power efficient signaling topology for driving the clocks to higher interconnect lengths.</p>

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“…Meng [4] presented a novel optimized policy to choose voltage-frequency settings for the execution mode of each core by utilizing predictions on a regression model while maintaining power and temperature constraints. Our prior work [5] presented a thermal-aware policy of dynamic frequency scaling bus (DFSB) for 3D Network-on-Chip (NoC) hybrid architectures. However, the DVFS-based thermal management system is an open-loop control system that requires accurate power measurement and limits the stability of the system.…”

Section: Introductionmentioning

confidence: 99%

Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

Shen

Gao

2020

Electronics

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By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

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DFSB-Based Thermal Management Scheme for 3-D NoC-Bus Architectures

Cited by 11 publications

References 36 publications

CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems

CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems

Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters

Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

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