DFE architectures for high-speed backplane applications

Li, M.; Wang, S.; Kwaśniewski, T.

doi:10.1049/el:20052206

Cited by 2 publications

(3 citation statements)

References 2 publications

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“…It should also be mentioned here that the forward equalizer need not necessarily take the form of a traditional FIR filter. As an alternative, a passive analog equalizer consisting of an L-R-C network can be used in order to reverse some of the frequency response of the channel [26], [27]. For this reason, in figure 2.8 the adaptation engine for the forward equalizer has been shown in grey as it may not necessarily be present.…”

Section: State O F the Artmentioning

confidence: 99%

“…Due to the timing requirements of the incoming data, the DFE filter must make use of high-speed circuitry and alternative configurations in order to operate effectively. These alternative configurations may include; half-rate topologies which reduce the timing con straints on each hardware block [27], [41], predictive first-tap feedback [25], [41], a senseamplifier based decision device [15], [24], and most importantly, common mode logic [24], [25], [27], Common mode logic or CML is commonly used in high-speed circuits due to the lower power consumption it exhibits compared to standard CMOS at high GHz Frequencies [28], The lower power consumption is due to the fact that it uses a lower volt age swing and a constant current which is switched within the gate. Further benefits from the CML structure are derived from its differential topology such as common mode noise immunity and compatibility with backplane signalling [29].…”

Section: State O F the Artmentioning

confidence: 99%

“…These benefits make CML type structures ideal for use in implementing the DFE filter. Figure 2.9 illustrates a typical modem filter structure which is similar to those used in [15], [24]- [25], [27]. In the above example, the present data is on input Dj while previous data is fed back from the decision device and delay elements (not shown) as the inputs D2 and D3.…”

Section: State O F the Artmentioning

confidence: 99%

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Blind adaptation of a decision feedback equalizer for use in a 10Gbps serial link

Berndt¹

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The Decision Feedback Equalizer (DFE) is commonly used in recovering data at the receive end of a multi-gigabit per second rate serial backplane channel. This form of equalization scheme typically relies on a training sequence. However this training sequence may not be shared by all implementations of the DFE, thus causing significant compatibility issues. A model of a DFE and adaptation algorithm was developed in MATLAB in combination with measurement data of a typical backplane channel. A method was developed to process the incoming signals from the channel involving a known adaptation algorithm in order to determine appropriate tap coefficients. These coefficients are shown to be effective for a data rate of 10 Gbps. The design presented would yield itself to standard-cell implementation except for the analog DFE structure and several stages of the up/down counters. Furthermore the design was evaluated using representative error sources and across several design parameters.Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.There are many people I would like to thank for their encouragement and support during the course of my degree. The first and foremost is my supervisor, Professor Tad Kwasniewski, for always guiding me with my best interests in mind and for creating an environment which is so ideal for learning. I would like to thank my research group, from which I have learned a great deal more than I had ever anticipated. To my friends in the department;

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Section: State O F the Artmentioning

confidence: 99%