Device Variation-Aware Adaptive Quantization for MRAM-based Accurate In-Memory Computing Without On-chip Training

Xing, Zhihua; Naik, V. B.; Cheung, Shun Kong; Lim, J. H.; Kwon, Jae‐Hyun; Ren, Zheyu; Wang, Zhongrui; Shao, Qiming

doi:10.1109/iedm45625.2022.10019482

2022 International Electron Devices Meeting (IEDM) 2022

DOI: 10.1109/iedm45625.2022.10019482

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Device Variation-Aware Adaptive Quantization for MRAM-based Accurate In-Memory Computing Without On-chip Training

Zhihua Xing

V. B. Naik

Shun Kong Cheung

et al.

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2024

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Cited by 3 publications

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“…Nonvolatile random-access memory (RAM) technologies such as resistive RAM, − phase change RAM, magnetoresistive RAM (MRAM), and ferroelectric RAM have been proven exceptionally suitable and successful in hardware-accelerated matrix multiplication, a burdensome operation predominant in AI training and computing, owing to their nonvolatility and crossbar structure. Nevertheless, matrix multiplication is just one side of the coin in stochastic neural networks.…”

mentioning

confidence: 99%

Restricted Boltzmann Machines Implemented by Spin–Orbit Torque Magnetic Tunnel Junctions

Li,

Wan,

Zhang

et al. 2024

Nano Lett.

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Artificial intelligence has surged forward with the advent of generative models, which rely heavily on stochastic computing architectures enhanced by true random number generators with adjustable sampling probabilities. In this study, we develop spin−orbit torque magnetic tunnel junctions (SOT-MTJs), investigating their sigmoid-style switching probability as a function of the driving voltage. This feature proves to be ideally suited for stochastic computing algorithms such as the restricted Boltzmann machines (RBM) prevalent in pretraining processes. We exploit SOT-MTJs as both stochastic samplers and network nodes for RBMs, enabling the implementation of RBM-based neural networks to achieve recognition tasks for both handwritten and spoken digits. Moreover, we further harness the weights derived from the preceding image and speech training processes to facilitate cross-modal learning from speech to image generation. Our results clearly demonstrate that these SOT-MTJs are promising candidates for the development of hardware accelerators tailored for Boltzmann neural networks and other stochastic computing architectures.

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mentioning

confidence: 99%

Restricted Boltzmann Machines Implemented by Spin–Orbit Torque Magnetic Tunnel Junctions

Li,

Wan,

Zhang

et al. 2024

Nano Lett.

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Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks

Wang,

Zhang

et al. 2024

IEEE Trans. Circuits Syst. II

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Adapting magnetoresistive memory devices for accurate and on-chip-training-free in-memory computing

Xiao,

Naik,

Lim

et al. 2024

Sci. Adv.

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Memristors have emerged as promising devices for enabling efficient multiply-accumulate (MAC) operations in crossbar arrays, crucial for analog in-memory computing (AiMC). However, variations in memristors and associated circuits can affect the accuracy of analog computing. Typically, this is mitigated by on-chip training, which is challenging for memristors with limited endurance. We present a hardware-software codesign using magnetic tunnel junction (MTJ)–based AiMC off-chip calibration that achieves software accuracy without costly on-chip training. Hardware-wise, MTJ devices exhibit ultralow cycle-to-cycle variations, as experimentally evaluated over 1 million mass-produced devices. Software-wise, leveraging this, we propose an off-chip training method to adjust deep neural network parameters, achieving accurate AiMC inference. We validate this approach with MAC operations, showing improved transfer curve linearity and reduced errors. By emulating large-scale neural network models, our codesigned MTJ-based AiMC closely matches software baseline accuracy and outperforms existing off-chip training methods, highlighting MTJ’s potential in AI tasks.

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Device Variation-Aware Adaptive Quantization for MRAM-based Accurate In-Memory Computing Without On-chip Training

Cited by 3 publications

References 2 publications

Restricted Boltzmann Machines Implemented by Spin–Orbit Torque Magnetic Tunnel Junctions

Restricted Boltzmann Machines Implemented by Spin–Orbit Torque Magnetic Tunnel Junctions

Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks

Adapting magnetoresistive memory devices for accurate and on-chip-training-free in-memory computing

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