Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks

Granular Magnetization Switching in Pt/Co/Ti Structure with HfOx Insertion for In-Memory Computing Applications

“…Conventional computers use the von Neumann architecture where the main memories are physically and functionally separated from the central processing unit (CPU). − The mismatch in processing speed and data transfer rate between the CPU and memory constrains the operational efficiency of conventional computers. Inspired by the human brain of storing and processing information concurrently, researchers exploit novel hardware architectures based on emerging nonvolatile memories to implement logic-in-memory architecture. ,− Compared with other memories, magnetoresistive random-access memory (MRAM) has become one of the most popular candidates for in-memory computing because of its low power consumption, infinite endurance, and nonvolatility. − The conventional MRAM device based on magnetic tunneling junction (MTJ) has binary states, which is not efficient for operating the multistate storage. , To achieve the multiple states, researchers have attempted to integrate multi-MTJ pillars into a single write-line. , Controlling the pillar individually switches to get multiple states, but this requires more MTJ pillars, which greatly increases the bit cell size . Another approach is to control the DW motion in the free layer of MTJ, causing the parallel and antiparallel composition change between the free layer and fixed layer to tune the output resistance. ,− Recently, the MTJ devices utilizing DW positions for in-memory computing, artificial synapse, and spiking neuron functionalities have been successfully demonstrated. − However, this method requires larger device sizes and complex device structures to produce multiple DW locations.…”

“…9−11 The conventional MRAM device based on magnetic tunneling junction (MTJ) has binary states, which is not efficient for operating the multistate storage. 11,12 To achieve the multiple states, researchers have attempted to integrate multi-MTJ pillars into a single writeline. 13,14 Controlling the pillar individually switches to get multiple states, but this requires more MTJ pillars, which greatly increases the bit cell size.…”