Device structures and carrier transport properties of advanced CMOS using high mobility channels

Takagi, Shinichi; Tezuka, T.; Irisawa, Toshifumi; Nakaharai, Shu; Numata, T.; Usuda, Koji; Sugiyama, N.; Shichijo, Masato; Nakane, Ryosho; Sugahara, Satoshi

doi:10.1016/j.sse.2007.02.017

Cited by 158 publications

(87 citation statements)

References 45 publications

(54 reference statements)

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“…1 Historically, a gradual increase in mobility has been obtained by reducing the size of the carrier channels, and later by the strain engineering of Si. More recently, the search has also focused on incorporating other materials with a mobility higher than that of Si in the channel.…”

Section: Introductionmentioning

confidence: 99%

Giant enhancement of n-type carrier mobility in highly strained germanium nanostructures

Murphy-Armando

Fahy

2011

Journal of Applied Physics

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First-principles electronic structure methods are used to predict the rate of n-type carrier scattering due to phonons in highly-strained Ge. We show that strains achievable in nanoscale structures, where Ge becomes a direct bandgap semiconductor, cause the phonon-limited mobility to be enhanced by hundreds of times that of unstrained Ge, and over a thousand times that of Si. This makes highly tensile strained Ge a most promising material for the construction of channels in CMOS devices, as well as for Si-based photonic applications. Biaxial (001) strain achieves mobility enhancements of 100 to 1000 with strains over 2%. Low temperature mobility can be increased by even larger factors. Second order terms in the deformation potential of the Γ valley are found to be important in this mobility enhancement. Although they are modified by shifts in the conduction band valleys, which are caused by carrier quantum confinement, these mobility enhancements persist in strained nanostructures down to sizes of 20 nm.

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Section: Introductionmentioning

confidence: 99%

Giant enhancement of n-type carrier mobility in highly strained germanium nanostructures

Murphy-Armando

Fahy

2011

Journal of Applied Physics

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“…The strain of SiGe layers depends on the chip layout (pattern dependency), shape of recess in the S/D region [63,64], the growth temperature, Ge content, dopant concentration, and high k-stack materials in the gate stack [27,65]. Ex-situ and in situ cleaning, and surface damages are important points for the quality of SiGe layers.…”

Section: Relationship Between the Strain In Sige And Process Parametementioning

confidence: 99%

Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs

Radamson

Kolahdouz

2015

J Mater Sci: Mater Electron

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“…Applying new channel materials, such as SiGe, [80][81][82] Ge, 83 and group III-V materials 84 (GaAs, InAs, InSb, and InGaAs), will improve the carrier mobility through effective mass modulation and subband structure engineering. 85 The guidelines for modulating effective mass are summarized as follows: 86 (1) heavier m z for reducing inversion-layer thickness and increasing C thickness inv:…”

Section: Applying New High-mobility Channelsmentioning

confidence: 99%

“…SOI structures on Si substrates can minimize the influence of impurities from the Si standard processing and apparatus, allowing for the combination with a Si platform. For the overall consideration of compatibility and short-channel immunity, the ultimate CMOS structure may resort to an ultrathin body or multigate device on an insulator with a combination of a III-V semiconductor nMOS and Ge pMOS, 84 as shown in Fig. 35.…”

Section: Group Iii-v Materials Channelsmentioning

confidence: 99%

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Song

Zhou

et al. 2011

Journal of Elec Materi

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The aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal-oxide-semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/ drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new highmobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III-V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.

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Device structures and carrier transport properties of advanced CMOS using high mobility channels

Cited by 158 publications

References 45 publications

Giant enhancement of n-type carrier mobility in highly strained germanium nanostructures

Giant enhancement of n-type carrier mobility in highly strained germanium nanostructures

Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

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