Development of thermal compression bonding with Non Conductive Paste for 3DIC fine pitch copper pillar bump interconnections

Chan, Chien-Feng; Tseng, Wen-Tsung; Huang, Huei-Nuan; Huang, Pin Cheng; Chan, Mu-Hsuan; Lin, Chun-Tang; Liu, Mark; Chiu, Chi-Hsin; Chiu, Steve; Ma, Mike

doi:10.1109/eptc.2011.6184439

Cited by 9 publications

(2 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Copper pillar bump is widely used in 3D integrated packaging because of their smaller packaging size, excellent electrical and mechanical properties [5][6][7][8]. Currently, the most advanced threedimensional integration technologies, such as HBM [9,10], CoWoS [11,12], Foveros [13,14], etc., use the diameter of copper pillar bumps of about of 20 μm, while in the field of Micro LED, the size of micro-interconnection has reached 10μm or even smaller [15][16][17][18]. This size will continue to shrink in the future.…”

Section: Introductionmentioning

confidence: 99%

Research on Ni3Sn4 intermetallic compound for 5μm diameter Cu/Ni/Sn-3.0Ag micro bumps

Dai

Zhang

Yan

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

for 5 μm diameter micro bumps, the interfacial intermetallic compounds (IMCs) seriously affects the interconnection performance of micro bumps. In this paper, we focused on the discussion of the growth and control mechanism of IMCs of 5um diameter micro bumps at different temperatures and durations. The growth mechanism and morphology of Ni3Sn4 IMC was studied. Through the EDS analysis of the cross-sectional micro bumps, it could be determined that the composition of the slender columnar crystal IMC was Ni3Sn4. When the heating temperature was higher than the melting point of Sn-3.0wt%Ag solder, the IMC would exhibit uneven and abnormal growth along the Sn grain boundary. Furthermore, the IMC growth and diffusion mechanisms of solid-solid and solid-liquid interface reaction were discussed respectively. Finally, based on the temperature and duration of the growth and evolution of the Ni3Sn4 IMC, we gave appropriate suggestions for the use of small-sized micro bumps.

show abstract

Section: Introductionmentioning

confidence: 99%

Research on Ni3Sn4 intermetallic compound for 5μm diameter Cu/Ni/Sn-3.0Ag micro bumps

Dai

Zhang

Yan

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Especially, to develop effective underfill methods for 3D is unavoidable to relieve mechanical stresses so that the reliabilities of interconnections can be enhanced [7][8][9][10]. However, 3D structure with a thin logic device as a bottom die and Wide I/O DRAM as a top die has a lot of challenges in its assembly process such as: (1) To achieve void less underfill formation under the thin logic die, (2) To prevent underfill resin creeping on the back side of the thin logic die not to affect the memory die stacking, (3) To fill space with the underfill resin under overhangs of the memory die when the memory die is larger than the logic die.…”

Section: Introductionmentioning

confidence: 99%

High density and reliable packaging technology with Non Conductive Film for 3D/TSV

Ono

Watanabe

Ishikawa

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

View full text Add to dashboard Cite

The innovative flip chip assembly process with Non Conductive Film (NCF) contributes to high density and reliable 3D/TSV integrations has been developed and demonstrated. The target package had two tier structure which consisted of a logic device and Wide I/O DRAM. The logic device was fabricated by via-middle process and accompanied with 1200 TSVs, a thickness of 50 μm and 40 μm / 50 μm bump pitch layout. Thermalcompression bonding method with Cu pillar was applied to both connections between the memory die and the logic die and between the logic die and an organic substrate so that the high reliability could be achieved. In this work, NCF laminated on substrates was selected as an underfill material to establish robust process for 3D integrations and to realize the cost effective assembly. As reliability test items, 1500-cycle temperature cycling test, 1000h high temperature storage test, 1000h high humidity test, 500h unbiased highly accelerated stress test and 300h pressure cooker test were performed. Furthermore, 28 nm logic device and Wide I/O DRAM were assembled into the 3D structure with this new technology and 12.8 GB/s transmission and 89 % reduction of I/O power compared to LPDDR3 were demonstrated.

show abstract

Assembly Process and Application Studies of Pre-Applied Underfill Non-Conductive Film (NCF) and Non-Conductive Paste (NCP) for Advanced Packages

Chowdhury

Guino

Shim

et al. 2021

2021 IEEE 71st Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

Development of thermal compression bonding with Non Conductive Paste for 3DIC fine pitch copper pillar bump interconnections

Cited by 9 publications

References 6 publications

Research on Ni<sub>3</sub>Sn<sub>4</sub> intermetallic compound for 5μm diameter Cu/Ni/Sn-3.0Ag micro bumps

Research on Ni<sub>3</sub>Sn<sub>4</sub> intermetallic compound for 5μm diameter Cu/Ni/Sn-3.0Ag micro bumps

High density and reliable packaging technology with Non Conductive Film for 3D/TSV

Assembly Process and Application Studies of Pre-Applied Underfill Non-Conductive Film (NCF) and Non-Conductive Paste (NCP) for Advanced Packages

Contact Info

Product

Resources

About