Development of Plate Infinite Element Method for Stress Analysis of Elastic Bodies with Singularities

Liu, D. S.; Cheng, Kuo-Liang; Zhuang, Zhen-Wei

doi:10.1017/jmech.2013.24

Cited by 3 publications

(1 citation statement)

References 19 publications

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“…Hence, WLUF was rich at the peripheral margin of the gap between the first chip and the Si substrate, as well as among the stacked chips. Figure 6 provides an enlarged view of the μ-bumps after chip stacking in both FEA [ 24 , 25 ] and the actual specimen. Figure 7 exhibits the detailed dimensions, components, and finite element mesh of the μ-bump framework used in the temperature cycling simulation.…”

Section: Failure Analysis and The Estimation Of Fatigue Lifetime Imentioning

confidence: 99%

Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests

Lee

2017

Materials

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The microbump (μ-bump) reliability of 3D integrated circuit (3D-IC) packaging must be enhanced, in consideration of the multi-chip assembly, during temperature cycling tests (TCT). This research proposes vehicle fabrications, experimental implements, and a nonlinear finite element analysis to systematically investigate the assembled packaging architecture that stacks four thin chips through the wafer level underfill (WLUF) process. The assembly of μ-bump interconnects by daisy chain design shows good quality. Results of both TCT data and the simulation indicate that μ-bumps with residual SnAg solders can reach more than 1200 fatigue life cycles. Moreover, several important design factors in the present 3D-IC package influence μ-bump reliability. Analytical results show that the μ-bump’s thermo-mechanical reliability can be improved by setting proper chip thickness, along with a WLUF that has a low elastic modulus and a small coefficient of thermal expansion.

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Section: Failure Analysis and The Estimation Of Fatigue Lifetime Imentioning

confidence: 99%

Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests

Lee

2017

Materials

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Accurate evaluation of mixed-mode intensity factors of cracked shear-deformable plates by an enriched meshfree Galerkin formulation

et al. 2016

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Prevention of Tape-Induced Si<sub>3</sub>N<sub>4</sub> Damage in Semiconductor Silicon Devices Encapsulated Utilizing Lead-on-Chip Packaging Technique

Lee

2021

Mater. Trans.

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This work details how thermal-cycling reliability degradation in semiconductor devices encapsulated utilizing a lead-on-chip (LOC) packaging technique is influenced by lead-frame tape structure modification. This work demonstrates through thermal-cycling testing that device pattern reliability is very sensitive to changes in the adhesive layer structure of the lead-frame tape. Particularly, in-situ examinations show that device failures result from fractures in the Si 3 N 4 layer, which comprises the top layer of semiconductor devices, due to the excessive thermal behavior of the adhesive layer during thermal-cycling. This work theoretically proves that, during temperature variation, the Cramer-von Mises stress as well as the shear stress, which has been known to be responsible for Si 3 N 4 damage, is proportionally related to a difference in the coefficient of thermal expansion (CTE) between the lead-frame tape (i.e., the adhesive layer) and the silicon device. Based on the experimental results and theoretical interpretation, this work concludes that, instead of the adhesive layer, an adhesive-filling base layer with a low CTE for lead-frame attachment on the device surface can help semiconductor devices to have better reliability margins in LOC packages.

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Development of Plate Infinite Element Method for Stress Analysis of Elastic Bodies with Singularities

Cited by 3 publications

References 19 publications

Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests

Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests

Accurate evaluation of mixed-mode intensity factors of cracked shear-deformable plates by an enriched meshfree Galerkin formulation

Prevention of Tape-Induced Si<sub>3</sub>N<sub>4</sub> Damage in Semiconductor Silicon Devices Encapsulated Utilizing Lead-on-Chip Packaging Technique

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