Development of Novel Filler Technology for No-Flow and Wafer Level Underfill Materials

Abstract

Flip chip technology is one of the fastest growing segments of electronic packaging with growth being driven by the demands such as cost reduction, increase of input/output density, package size reduction and higher operating speed requirements. Unfortunately, flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate, which leads to premature failures of the package. Package reliability can be improved by the application of an underfill. In this paper, we report the development of novel underfill materials utilizing nano-filler technology, which provides a previously unobtainable balance of low CTE and good solder joint formation.

Encapsulation Process Technology

“…Silica fi llers are absent from the encapsulant because they can interfere with solder joint formation. Innovative methods have been developed to allow the addition of silica fi llers to no-fl ow underfi lls without compromising solder joint formation, such as double-layer no-fl ow underfi lling and nano-fi ller technology [24,25]. No-fl ow underfi lling can also be more expensive [26].…”

Development of No-flow Underfill Materials and Processes for Pb-free Flip Chip Applications

“…This difficulty has been circumvented through the introduction of a more complex process involving a twolayer no-flow adhesive application [7]. The authors have also reported development of a nanofilled no-flow underfill material, for Sn/Pb based flip chip devices, to overcome the problems posed by large filler particles [8].…”