Development of low-noise high value chromium silicide resistors for cryogenic detector applications

Jhabvala, M.; Babu, R. Sachidananda; Monroy, C.; Freund, Minoru M.; Dowell, C. D.

doi:10.1016/s0011-2275(02)00078-4

Cited by 13 publications

(13 citation statements)

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“…Chromium, silicon, and their alloys are very important materials in the manufacture of thin film resistors and microelectronic devices. [51][52][53][54] It has been suggested that chromium silicide is a potentially important contact material in future nanosystems because chromium silicide nanostructures can reduce the energy barrier between the metal and semiconductor layers. 55 Chromium-doped silicon clusters have been studied by many researchers.…”

Section: Introductionmentioning

confidence: 99%

Structures and magnetic properties of CrSin− (n = 3–12) clusters: Photoelectron spectroscopy and density functional calculations

Kong

Zheng

2012

The Journal of Chemical Physics

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Chromium-doped silicon clusters, CrSi(n)(-) (n = 3-12), were investigated with anion photoelectron spectroscopy and density functional theory calculations. The combination of experimental measurement and theoretical calculations reveals that the onset of endohedral structure in CrSi(n)(-) clusters occurs at n = 10 and the magnetic properties of the CrSi(n)(-) clusters are correlated to their geometric structures. The most stable isomers of CrSi(n)(-) from n = 3 to 9 have exohedral structures with magnetic moments of 3-5μ(B) while those of CrSi(10)(-), CrSi(11)(-), and CrSi(12)(-) have endohedral structures and magnetic moments of 1μ(B).

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Section: Introductionmentioning

confidence: 99%

Structures and magnetic properties of CrSin− (n = 3–12) clusters: Photoelectron spectroscopy and density functional calculations

Kong

Zheng

2012

The Journal of Chemical Physics

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“…The resistance of a single gold bond wire, including contact resistance, can be less than 10 mΩ at low temperatures [46]. On the other hand, the electrical resistance can easily be increased above 10 kΩ by including onchip thin-film resistors or tunnel junctions [47][48][49][50].…”

Section: Thermal Modelmentioning

confidence: 99%

Progress in Cooling Nanoelectronic Devices to Ultra-Low Temperatures

et al. 2020

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Here we review recent progress in cooling micro-/nanoelectronic devices significantly below 10 mK. A number of groups worldwide are working to produce submillikelvin on-chip electron temperatures, motivated by the possibility of observing new physical effects and improving the performance of quantum technologies, sensors and metrological standards. The challenge is a longstanding one, with the lowest reported on-chip electron temperature having remained around 4 mK for more than 15 years. This is despite the fact that microkelvin temperatures have been accessible in bulk materials since the mid-twentieth century. In this review, we describe progress made in the last 5 years using new cooling techniques. Developments have been driven by improvements in the understanding of nanoscale physics, material properties and heat flow in electronic devices at ultralow temperatures and have involved collaboration between universities and institutes, physicists and engineers. We hope that this review will serve as a summary of the current state of the art and provide a roadmap for future developments. We focus on techniques that have shown, in experiment, the potential to reach sub-millikelvin electron temperatures. In particular, we focus on on-chip demagnetisation refrigeration. Multiple groups have used this technique to reach temperatures around 1 mK, with a current lowest temperature below 0.5 mK.

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“…Next, a lift-off process is used to pattern sputtered chrome silicide resistive lines. Chrome silicide is used because it is compatible with the fabrication process steps and has one of the highest sheet resistances reported in thin film resistors [5][6][7][8]. The 30-nm-thick chrome silicide resistive layer was experimentally proven to not affect the microwave loss of the filter.…”

Section: Fabricationmentioning

confidence: 99%

“…Another class of fast algorithms is the fast Fourier transform (FFT)-based methods, such as the adaptive integral method (AIM) [5,6] and the precorrected FFT (P-FFT) [7], [8]. With the help of FFT, both the AIM and the P-FFT can reduce the memory requirement to O(N 1.5 ) and computational complexity to O(N 1.5 log N) for three-dimensional (3D) perfectly electric conducting (PEC) scattering problems.…”

Section: Introductionmentioning

confidence: 99%

Low‐loss MEMS switchable microstrip filters

Ong¹,

Okoniewski²

2008

Micro & Optical Tech Letters

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tors. The quadrature ILFD uses the 3D inductors to save chip area and the ILFD has been successfully implemented in the TSMC 0.18-m CMOS process. At the supply voltage of 0.9 V, the core power consumption of the proposed circuit is about 9.36 mW. At the input power of Ϫ8 dBm, the total operation locking range is 2.45 GHz, from 3.6 to 6.05 GHz, in the Ϭ2 mode. The phase deviation between in-phase and quadrature-phase outputs is about 0.19°. ACKNOWLEDGMENTThe authors thank the CIC of National Science Council, ROC, for the chip implementation. REFERENCES 1. H. Wu and A. Hajimiri, A 19 GHz 0.5 mW 0.35 m CMOS frequency divider with shunt-peaking locking-range enhancement, In: ISSCC Digest of Technical Papers, Feb. 2001, pp. 412-413. 2. M. Tiebout, A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider, IEEE J Solid-State Circuits 39 (2004), 1170 -1174. 3. P. Andreani and X. Wang, On the phase-noise and phase-error performances of multiphase LC CMOS VCOs, IEEE J Solid-State Circuits 39 ABSTRACT: Parallel-coupled microstrip filters with MEMS switchable frequency responses are designed. The 15-GHz filter switches 5.3% with minimum insertion loss of 0.7 dB, whereas the 20-GHz filter has 12.9% switching range and minimum insertion loss of 0.6 dB. Both filters have the lowest insertion losses among MEMS tunable microwave bandpass filters to date. ABSTRACT: A fast integral equation method, termed IE-FFT, is applied with the combined field integral equation (CFIE) for solving electromagnetic scattering problems of three-dimensional (3D) electrically large targets. For closed conducting surfaces, the employment of CFIE eliminates the internal resonance problem suffered by both the electric field integral equation and the magnetic integral equation. Furthermore, it improves the efficiency of IE-FFT significantly by reducing the number of iterations for convergence. It is shown that the memory requirement and the computational complexity per iteration of the IE-FFT are O(N 1.5 ) and O(N 1.5 log N), respectively, for 3D perfectly electric conducting scattering problems. Some numerical examples are provided to demonstrate the accuracy and efficiency of the technique.

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Development of low-noise high value chromium silicide resistors for cryogenic detector applications

Cited by 13 publications

References 1 publication

Structures and magnetic properties of CrSin− (n = 3–12) clusters: Photoelectron spectroscopy and density functional calculations

Structures and magnetic properties of CrSin− (n = 3–12) clusters: Photoelectron spectroscopy and density functional calculations

Progress in Cooling Nanoelectronic Devices to Ultra-Low Temperatures

Low‐loss MEMS switchable microstrip filters

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