Development of High-efficiency Industrial p-type Multi-crystalline PERC Solar Cells with Efficiency Greater Than 21%

21.63% industrial screen-printed multicrystalline Si solar cell

“…The cell shows an efficiency ( η ) of 21.63%, an open circuit voltage ( V oc ) of 671.4 mV, a short circuit current ( I sc ) of 9.952 A (current density J sc = 40.56 mA/cm 2 ) and a fill factor (FF) of 79.44. Compared to the previous best report by Deng et al , our cell demonstrates superior efficiency, V oc and I sc . In fact, to the best of our knowledge, the cell efficiency appears to be the best reported result so far for large area (>156 mm × 156 mm), industrial grade low cost p ‐ type mc‐Si solar cells.…”

“…Additionally, the same front contacting pattern as the one used to fabricate conventional mc‐Si cells at JinkoSolar was used. This contacting pattern has an optical shading of ∼4%, which is larger than the one reported by Deng et al based on their photoluminescence image . As a result, this can be further optimized to increase the I sc and V oc , and thus cell efficiency.…”

“…All recombination parameters for the metal contacted and passivated area for both front and rear surfaces are summarized in Table . The typical values of J 0‐contacted for the front and rear are obtained from literature for a 90 Ω/□ phosphorus and Al‐BSF .…”

“…PERC remains competitive due to its processing simplicity and thus feasibility for low cost Si solar cells manufacturing. The current highest recorded efficiency for large area (156 mm × 156 mm) p‐type mc‐Si PERC cell is 21.25%, as reported by Deng et al at TrinaSolar in September 2016 . In this paper, based on novel cell fabrication approaches, and the independent measurement carried out by the Solar Energy Research Institute of Singapore (SERIS), we report an even higher efficiency at 21.63%, for (156.65 mm × 156.65 mm) p‐type mc‐Si PERC cell.…”

Conductive Hole‐Selective Passivating Contacts for Crystalline Silicon Solar Cells

“…After spin‐coating, the thin films needed a low‐temperature (100−130 °C) bake in an ambient atmosphere. Before the PEDOT:Nafion coating process, the standard industrial processes were used for multicrystalline silicon solar cells [ 58 ] for surface texturing through metal‐catalyzed chemical etching (MCCE), [ 59 ] the p−n junction, the surface antireflection layer, the front metallization POCl 3 gas source diffusion, PECVD, and screen‐printing technologies. The wafers used met industrial specifications; they were p‐type, multicrystalline, and had a resistivity of ≈1.5 Ω·cm and thickness of 180 µm by diamond wire cutting.…”