Development of Data Concentration Method and Its Implementation in a Radiation-Tolerant CMOS Application Specific Integrated Circuit

Azarov, D. A.; Normanov, D.; Ivanov, P.; Samsonov, V.; Serazetdinov, A. R.; Shumikhin, V.

doi:10.1134/s1063779621040080

Search citation statements

Order By: Relevance

Paper Sections

Select...

Jinst 17 C070061

Introduction1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2022

Publication Types

Select...

Article1

Relationship

Self Cite1

Independent0

Authors

Journals

Cited by 1 publication

(2 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The first application of ADCG is planned as a part of a phase-locked loop for a data concentrator ASIC [2] intended for a time-projection chamber of Multi-Purpose Detector at NICA, Dubna.…”

Section: Jinst 17 C07006mentioning

confidence: 99%

See 1 more Smart Citation

A low power clock generator 400–1800 MHz for ADPLL

Ivanov¹,

Normanov²

2022

J. Inst.

Self Cite

View full text Add to dashboard Cite

This paper describes a low-power all-digital clock generator (ADCG) designed for reading and processing signals from detectors of large physical experiments. The clock generator operates with a reference clock frequency of 10 to 50 MHz and generates an output signal ranging from 400 to 1800 MHz in 10 MHz steps. The clock generator has been approved in 28 nm CMOS technology of TSMC. The power consumption and chip area of the block are 1.5 mW and 80 × 80 μm2 correspondingly. A wide range of reference and output frequencies makes this block versatile in application.

show abstract

“…The first application of ADCG is planned as a part of a phase-locked loop for a data concentrator ASIC [2] intended for a time-projection chamber of Multi-Purpose Detector at NICA, Dubna.…”

Section: Jinst 17 C07006mentioning

confidence: 99%

“…At present our team continues the development of the interpolator ASIC in 180 nm UMC process intended for CBM experiment at FAIR as well as the data concentrator ASIC in 65 nm TSMC process for MPD experiment at NICA [1][2][3]. Both ASICs contain phase locked-loop (PLL) blocks, working in different frequency ranges.…”

Section: Introductionmentioning

confidence: 99%