Development of an FPGA-Based Data Acquisition Module for Small Animal PET

Imrek, J.; Novák, D.; Hegyesi, Gyula; Molnár, J.; Végh, János; Balkay, László; Emri, Miklós; Molnar, Goran; Trón, Lajos; Bagamery, I.; Bükki, Tamás; Rozsa, S.; Szabó, Z.; Kerek, A.

doi:10.1109/tns.2006.876004

Cited by 30 publications

(19 citation statements)

References 11 publications

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“…This is easier with a single DAQ board or when all DAQ boards are within the same crate; in this case, synchronization is usually achieved with a system-synchronous clocking scheme, where a simple clock tree is implemented using clock buffers and then distributed to all DAQ boards through controlled backplane connections. Clock skew and jitter figures are rarely documented [9], although they can occasionally be inferred [10]. Sometimes, a combined systemwide skew and jitter figure is given [11], [12].…”

Section: Introductionmentioning

confidence: 99%

PET System Synchronization and Timing Resolution Using High-Speed Data Links

Aliaga

Monzó

Spaggiari

et al. 2011

IEEE Trans. Nucl. Sci.

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Abstract-Current PET systems with fully digital trigger rely on early digitization of detector signals and the use of digital processors, usually FPGAs, for recognition of valid gamma events on single detectors. Timestamps are assigned and later used for coincidence analysis. In order to maintain a decent timing resolution for events detected on different acquisition boards, it is necessary that local timestamps on different FPGAs be synchronized. Sub-nanosecond accuracy is mandatory if we want this effect to be negligible on overall timing resolution. This is usually achieved by connecting all boards to a common backplane with a precise clock delivery network; however, this approach forces a rigid structure on the whole PET system and may pose scalability problems.As an alternative, we propose a backplane-less PET system architecture in which DAQ boards are connected by single fullduplex high-speed data links. Data encoding with embedded clock is used to correct frequency differences between local oscillators. Timestamp synchronization between FPGAs with clock period resolution is maintained by means of data transfers in a way similar to the IEEE 1588 standard. Finer resolution is achieved by reflection of received clocks and phase difference measurement on the transmitter. It is crucial that data transceivers have very low latency uncertainty in order to achieve the desired timestamp accuracy; we discuss the availability of off-the-shelf hardware for these implementations.

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Section: Introductionmentioning

confidence: 99%

PET System Synchronization and Timing Resolution Using High-Speed Data Links

Aliaga

Monzó

Spaggiari

et al. 2011

IEEE Trans. Nucl. Sci.

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“…While CFDs can achieve sub-nanosecond timing resolution [5], FPGAs have made advancements in computing power and I/O sophistication that may allow them to achieve similar timing results. There have been previous efforts to perform the timing pickoff in the FPGA.…”

Section: Timing Algorithmsmentioning

confidence: 99%

“…While CFDs can achieve sub-nanosecond timing resolution, FPGAs have made advancements in computing power and I/O sophistication that may allow them to achieve similar timing results. Many current PET systems already utilize FPGAs for data acquisition [4,5], so it is logical to employ the already used circuit board area to compute the timing pickoff. In addition to removing the need for separate analog timing components, FPGA based timing allows many channels to be processed by a single timing circuit instead of one circuit per channel.…”

Section: Introductionmentioning

confidence: 99%

Simulation of algorithms for pulse timing in FPGAs

Haselman

Hauck

Lewellen

et al. 2007

2007 IEEE Nuclear Science Symposium Conference Record

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Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates well above 100MHz. This, combined with FPGA's low expense and ease of use, make them an ideal technology for pulse timing and are a central part of our next generation of electronics for our pre-clinical PET scanner systems. To that end, our laboratory has been developing a pulse timing technique that uses pulse fitting to achieve timing resolution well below the sampling period of the analog to digital converter (ADC). While ADCs with sampling rates in excess of 400MS/s exist, we feel that using ADCs with lowing sampling rates has many advantages for positron emission tomography (PET) scanners. It is with this premise that we have started simulating timing algorithms using MATLAB in order to optimize the parameters before implementing the algorithm in Verilog. MATLAB simulations allow us to quickly investigate filter designs, ADC sampling rates and algorithms with real data before implementation in hardware. We report our results for a least squares fitting algorithm and a new version of a leading edge detector of PMT pulses.

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“…Many groups have exploited the use of FPGAs for pulse processing in scanner electronics [e.g, [6][7][8][9]. In our own laboratory, the FPGAs are routinely used for pulse integration [1,12] and we are developing implementations for statistical event localization [2] and timing [5].…”

Section: Introductionmentioning

confidence: 99%

Design of a second generation firewire based data acquisition system for small animal PET scanners

Lewellen

Miyaoka

MacDonald

et al. 2008

2008 IEEE Nuclear Science Symposium Conference Record

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The University of Washington developed a Firewire based data acquisition system for the MiCES small animal PET scanner. Development work has continued on new imaging scanners that require more data channels and need to be able to operate within a MRI imaging system. To support these scanners, we have designed a new version of our data acquisition system that leverages the capabilities of modern field programmable gate arrays (FPGA). The new design preserves the basic approach of the original system, but puts almost all functions into the FPGA, including the Firewire elements, the embedded processor, and pulse timing and pulse integration. The design has been extended to support implementation of the position estimation and DOl algorithms developed for the cMiCE detector module. The design is centered around an acquisition node board (ANB) that includes 65 ADC channels, Firewire 1394b support, the FPGA, a serial command bus and signal lines to support a rough coincidence window implementation to reject singles events from being sent on the Firewire bus. Adapter boards convert detector signals into differential paired signals to connect to the ANB.

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Development of an FPGA-Based Data Acquisition Module for Small Animal PET

Cited by 30 publications

References 11 publications

PET System Synchronization and Timing Resolution Using High-Speed Data Links

PET System Synchronization and Timing Resolution Using High-Speed Data Links

Simulation of algorithms for pulse timing in FPGAs

Design of a second generation firewire based data acquisition system for small animal PET scanners

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