Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues

Soares, André Borin; Bonatto, Alexsandro Cristóvão; Susin, Altamiro

doi:10.1155/2013/783501

Cited by 4 publications

(3 citation statements)

References 10 publications

(14 reference statements)

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“…The simulated STB is composed from several processing units and this case study combines six memory clients accessing one DRAM channel, as described before in [13]. A Leon-3 CPU (SPARC-v8 ISA) [11] is connected to the memory subsystem through one level of data/instruction cache (L1), with block size of 32 bytes configured as 1, 2 or 4-way.…”

Section: Methodsmentioning

confidence: 99%

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Adaptive Shared Memory Control for Multimedia Systems-on-Chip

Bonatto

Negreiros

Pereira

et al. 2014

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

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Memory subsystem is a major concern in the design of multimedia systems and the memory performance may become the bottleneck for the overall processing performance. This work presents a memory subsystem implementation with adaptive control for access to shared memory in multimedia Systems-on-Chip (SoC). A memory-centric design approach is used to implement the memory subsystem for the purpose of meet bandwidth and deadline requirements of the heterogeneous processing elements. A latency-based model is obtained based on the Worst-Case Response Time (WCRT) criterion. In the presented approach, an adaptive arbiter is designed and implemented to control memory access requests targeting to comply with clients' deadline requirements managing data latency of accesses. Also, an algorithmic implementation of the adaptive arbitration control is presented and evaluated. This paper presents hardware implementation results for the proposed memory subsystem with an adaptive arbiter control. Our proposal of simple estimation of WCRT leads to a hardware implementation with low latency calculation of the system limits imposed to clients. This way the proposed adaptation approach can be implemented at run-time.

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Section: Methodsmentioning

confidence: 99%

“…Table 2 presents the parameters used in this analysis, obtained from the hardware simulation behavior presented in [4,13]. The testbench used is composed by procedures described in VHDL to generate reads and writes simulating the memory access behavior for the digital television STB.…”

Section: Methodsmentioning

confidence: 99%

Adaptive Shared Memory Control for Multimedia Systems-on-Chip

Bonatto

Negreiros

Pereira

et al. 2014

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

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show abstract

“…set-top box, smart phone), targeted at broadcast/video streaming applications. Main memory data traffic of dependent picture buffer (DPB) access has shown to impact realtime display of high definition (HD) video sequences (Soares et al, 2013). Furthermore, multiple reference frames can linearly increase the memory usage of the decoder (Saponara et al, 2004).…”

Section: Encoder and Decoder Settingsmentioning

confidence: 99%

Synthetic Workload Generation of Broadcast Related HEVC Stream Decoding for Resource Constrained Systems

Mendis

Indrusiak

2016

Proceedings of the 13th International Joint Conference on E-Business and Telecommunications

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Performance evaluation of platform resource management protocols, require realistic workload models as input to obtain reliable, accurate results. This is particularly important for workloads with large variations, such as video streams generated by advanced encoders using complex coding tools. In the modern High Efficiency Video Coding (HEVC) standard, a frame is logically subdivided into rectangular coding units. This work presents synthetic HEVC decoding workload generation algorithms classified at the frame and coding unit levels, where a group of pictures is considered as a directed acyclic graph based taskset. Video streams are encoded using a minimum number of reference frames, compatible with low-memory decoders. Characteristic data from several HEVC video streams, is extracted to analyse inter-frame dependency patterns, reference data volume, frame/coding unit decoding times and other coding unit properties. Histograms are used to analyse their statistical characteristics and to fit to known theoretical probability density functions. Statistical properties of the analysed video streams are integrated into two novel algorithms, that can be used to synthetically generate HEVC decoding workloads, with realistic dependency patterns and frame-level properties.

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Methods to develop high throughput hardware architectures for HEVC Deblocking Filter using mixed pipelined-block processing techniques

Kopperundevi

Prakash

2022

Microelectronics Journal

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Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues

Cited by 4 publications

References 10 publications

Adaptive Shared Memory Control for Multimedia Systems-on-Chip

Adaptive Shared Memory Control for Multimedia Systems-on-Chip

Synthetic Workload Generation of Broadcast Related HEVC Stream Decoding for Resource Constrained Systems

Methods to develop high throughput hardware architectures for HEVC Deblocking Filter using mixed pipelined-block processing techniques

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