Development of a new Package-on-Package (PoP) structure for next-generation portable electronics

Abstract

Package-on-Package (PoP) is one of the major 3D packaging approaches. It vertically combines discrete memory and logic Ball Grid Array (BGA) packages, where one package rests on the top of the other. Recently, PoP technologies have attracted more interests, especially for portable electronics related products and applications.ASTRI has developed a new PoP structure, which employs a new bottom package which is over molded Finepitch Ball Gird Array (FBGA) format with mechanically balanced package structure. For the top package, it is a commercial FBGA format with two die stacked inside. Since the new bottom package structure is based on an existing FBGA format, the mold chase is independent of the mold cap and size of the bottom PoP package. The final mold layer for bottom package has a thickness of 0.50mm. The top interface of the bottom PoP package has 136 pads with 0.65mm pitch and a two-row peripheral format, while the bottom interface has 272 pads with 0.65mm pitch and a four-row peripheral format. The size of both top and bottom packages is 14 x 14mm 2 . The 3D finite element (FE) simulator Ansoft HFSS was used to evaluate the high-frequency performance of the new PoP structure. The low-loss and low cross-coupling results indicate that the above PoP offers a promising solution for communication-related products. Physical configuration of the package was evaluated by cross section & scanning electron microscopy (SEM) examination, which showed a favorable interconnection structure. The warpage of the bottom PoP package after assembly process was characterized by a shadow moiré system. The warpage was well controlled by adopting a fully molded structure. The average package warpage value was around 30μm that was well below the warpage target of 80μm widely used in the industry. In this work, the moisture sensitivity level-3 (MSL-3) test was applied to evaluate the reliability of the above package. Board-level reliability including temperature cycling (TC) & drop tests were also evaluated. The results of the reliability tests showed good performance and demonstrated that the above PoP is a viable design. In summary, the above PoP design exhibited promising RF performance, excellent warpage performance, qualified package-level and boardlevel reliability. It offers an effective solution for high-density packages used in the portable consumer electronics.

Experimental and theoretical analyses of package-on-package structure under three-point bending loading

“…Also, the experimental process is shown by using in-situ scanning electron microscopy (SEM ) observation technol-ogy in order to obtain the micro failure mode of the structure. [18,20−22] The PoP structure consists mainly of the following parts: [23] (i) a top package for the memory unit in stack chip scale package format with three dies equidistantly implanted into the plastic resin and a thick substrate in the bottom; a bottom package for logic operation in over-molded FBGA format with a die embedded into the plastic resin and a thick substrate;…”

Survey of Reliability Research on 3D Packaged Memory

“…With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from 2D planar packaging structures to 3D packaging structures. Well-known memory manufacturers, such as Samsung Electronics, Micron, and SK hynix, have further improved the performance of memory devices via the use of 3D packaging technologies, such as PoP (package on package) [1][2][3], CoC (Chipon-Chip) [4][5][6], WLP (Wafer Level Package) [7][8][9], TSV (through-silicon via) [10][11][12], and Embedded Substrate [13][14][15], meeting the industry demands for high-frequency, highspeed, and large-capacity devices with low power consumption.…”

Compensation Method for Die Shift Caused by Flow Drag Force in Wafer-Level Molding Process

“…WLP technology possesses the advantages of fan-out packaging expandability and input/output increases, as the package bump extends to the external region of the silicon chip while allowing for WLP. This technology has the following characteristics [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 ]. WLP is achieved by implementing a 3D package, and it enables performance enhancement through a high pin count, an extension of existing silicon technologies, a reduction in device size, and a reduction in wiring delay.…”