Development and characterisation of a 3D technology including TSV and Cu pillars for high frequency applications

Abstract

As 3D packaging technologies are becoming more and more present in packaging roadmap, applications with higher requirement are rising continuously.Today, one of the main applications requiring 3D technologies is dedicated to nomadic components, including mobile phones, due to their very high compacity and integration capabilities. Those components need to work at high frequency, typically up to 1 GHz. For these frequencies, the resistance and the capacitance of the interconnections have to be minimized, in order to decrease the signal delay. This is a real challenge for 3D integration and especially for post process through silicon vias.In the first part of the paper, a study and a simple model to determine the main parameters responsible for resistance and parasitic capacitance variation will be presented. Then, a technical focus will be done on the improvement of the TSV electrical performances, especially the decreasing of the TSV parasitic capacitance from 2.41 pF to 0.76 pF based on Plasma Enhanced Chemical Vapour Deposition (PECVD) process development. Finally, the integration of this new material on a technological test vehicle with electrical results will be presented and discussed.

TSV last for hybrid pixel detectors: Application to particle physics and imaging experiments

“…The core technology of 3D integration is the TSV (Through Silicon Via) and for many years LETI has developed those technologies for various types of applications [4,5,6]. In this paper we will present how one of the TSV approaches developed by LETI, called TSV last, has been applied to a readout wafer containing readout chips intended for a hybrid pixel detector assembly [7,8].…”

“…A Deep Reactive Ion Etch (DRIE) Bosch process is used to form the 120 µm deep TSV cavities (Fig 9). A PECVD insulation oxide layer (SiH 4 precursor) is then deposited to ensure a full insulation of the TSV sidewalls [6]. The conformity of the sidewall is such that the layer thickness near the bottom of the sidewall is about 20% of that on top.…”

“…The TSV last technology is very flexible and can be applied to many domains and applications [3,6]. A simplified process flow diagram is presented in figure 5.…”

“…In the field of radiation imaging detectors the advantages of 3D Integration come from reduced inter chip dead area even on large surfaces and from improved detector construction yield resulting from the use of single chip 4-side buttable tiles [2]. For many years, numerous R&D centres and companies have put a lot of effort into developing 3D integration technologies and today, some mature technologies are ready for prototyping and production [3].The core technology of 3D integration is the TSV (Through Silicon Via) and for many years LETI has developed those technologies for various types of applications [4,5,6]. In this paper we will present how one of the TSV approaches developed by LETI, called TSV last, has been applied to a readout wafer containing readout chips intended for a hybrid pixel detector assembly [7,8].…”

Reliability study of 3D-WLP through silicon via with innovative polymer filling integration

“…In this case, TSV process is performed on the wafer back-side, after the back-end process on the front-side (figure 1) [4]. The wafer is bonded on a temporary glass carrier and thinned down to 120µm.…”