Reliability study of 3D-WLP through silicon via with innovative polymer filling integration

Bouchoucha, Mohamed Khalil; Chausse, P.; Moreau, S.; Chapelon, L.L.; Sillon, N.; Thomas, O.

doi:10.1109/ectc.2011.5898568

Cited by 18 publications

(2 citation statements)

References 5 publications

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“…However, it is not easy to achieve a polymer liner since its high viscosity will cause bad filling ability to achieve a uniform and continuous film on the sidewall of TSV. Therefore, polymer is usually served as filler for Cu liner TSV to reduce the residual stress and the concern of reliability [4]. In this study, a new process of polymer liner is developed to overcome this challenge.…”

Section: Introductionmentioning

confidence: 99%

Polymer TSV fabrication scheme with its electrical and reliability test vehicle

Lee

Shih

Chuang

et al. 2014

2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

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In this research, a novel process scheme for polymer TSV fabrication is proposed to solve the difficulty of polymer liner formation in TSV technology. The corresponding structure shows great manufacturability to replace traditional fabrication approach. In addition, Kelvin structure of the daisy chain is designed for evaluating electrical performance and reliability. Moreover, daisy chain with dummy TSV is designed to verify the impact of TSV pitch on TSV fabrication by using electrical measurement. The reliability tests include thermal cycling and humidity test to verify the quality of proposed polymer TSV design. Finally, a void-free polymer TSV with uniform liner formation is successfully fabricated and demonstrated.

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Section: Introductionmentioning

confidence: 99%

Polymer TSV fabrication scheme with its electrical and reliability test vehicle

Lee

Shih

Chuang

et al. 2014

2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

View full text Add to dashboard Cite

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“…The current issue and full text archive of this journal is available at www.emeraldinsight.com/0954-0911.htm The authors would also like to acknowledge the financial support of the Innovative electronic Manufacturing Research Centre (IeMRC) through the flagship project "Smart microsystems", referenced FS/01/02/10. requirements (Bouchoucha et al, 2011), make wafer-level packaging a key technology for next generation assembly and packaging roadmaps. For this reason it is gaining increasing levels of adoption in many industrial sectors, including automotive, consumer, and telecommunication applications.…”

Section: Introductionmentioning

confidence: 99%

Statistical analysis of stencil technology for wafer-level bumping

Kay

Cummins²,

Krebs

et al. 2014

Soldering &Amp; Surface Mount Technology

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Purpose – Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies: laser cutting, DC electroforming and micro-engineered electroforming. This investigation looks at stencil differences in printability, pitch resolution, maximum achievable bump height, print co-planarity, paste release efficiency, and cleaning frequency. The paper aims to discuss these issues. Design/methodology/approach – In this paper, the authors present a statistical evaluation of the impact of stencil technology on type-6 tin-silver-copper paste printing. The authors concentrate on performances at 200 and 150 μm pitch of full array patterns. Key evaluated criteria include achievable reflowed bump heights, deposit co-planarity, paste release efficiency, and frequency of stencil cleaning. Box plots were used to graphically view print performance over a range of aperture sizes for the three stencil types. Findings – Fabrication technologies significantly affect print performance where the micro-engineered electroformed stencil produced the highest bump deposits and the lowest bump height deviation. Second in performance was the conventional electroformed, followed by the laser-cut stencil. Comparisons between the first and fifth consecutive print demonstrated no need for stencil cleaning in the case for the micro-engineered stencil for all but the smallest spacings between apertures. High paste transfer efficiencies, i.e. above 85 per cent, were achieved with the micro-engineered stencil using low aperture area ratios of 0.5. Originality/value – Stencil technology influences the maximum reflowed solder bump heights achievable, and bump co-planarity. To date, no statistical analysis comparing the impact of stencil technology for wafer-level bumping has been carried out for pitches of 200 μm and below. This paper gives new insight into how stencil technology impacts the print performance for fine pitch stencil printing. The volume of data collected for this investigation enabled detailed insight into the limitations of the printing process and as a result for suitable design guidelines to be developed. The finding also shows that the accepted industry guidelines on stencil design developed by the surface mount industry can be broken if the correct stencil technology is selected, thereby increasing the potential application areas of stencil printing.

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Inkjet printing technology for increasing the I/O density of 3D TSV interposers

et al. 2017

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Interposers with through-silicon vias (TSVs) play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems. In the current practice of fabricating interposers, solder balls are placed next to the vias; however, this approach requires a large foot print for the input/output (I/O) connections. Therefore, in this study, we investigate the possibility of placing the solder balls directly on top of the vias, thereby enabling a smaller pitch between the solder balls and an increased density of the I/O connections. To reach this goal, inkjet printing (that is, piezo and super inkjet) was used to successfully fill and planarize hollow metal TSVs with a dielectric polymer. The under bump metallization (UBM) pads were also successfully printed with inkjet technology on top of the polymer-filled vias, using either Ag or Au inks. The reliability of the TSV interposers was investigated by a temperature cycling stress test (−40°C to +125°C). The stress test showed no impact on DC resistance of the TSVs; however, shrinkage and delamination of the polymer was observed, along with some micro-cracks in the UBM pads. For proof of concept, SnAgCu-based solder balls were jetted on the UBM pads.

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Reliability study of 3D-WLP through silicon via with innovative polymer filling integration

Cited by 18 publications

References 5 publications

Polymer TSV fabrication scheme with its electrical and reliability test vehicle

Polymer TSV fabrication scheme with its electrical and reliability test vehicle

Statistical analysis of stencil technology for wafer-level bumping

Inkjet printing technology for increasing the I/O density of 3D TSV interposers

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