Development and attributes of z/Architecture

Abstract

The IBM z/Architecture TM instruction set architecture (ISA) is an extension of the IBM Enterprise Systems Architecture/390 ® (ESA/390) ISA and features 64-bit general registers, 64-bit operations, and 64-bit virtual and real addressing. In addition, z/Architecture includes new instructions to optimize the handling of modern multi-byte character encodings and to improve the performance of programs written in high-level languages. It provides compatibility for ESA/390 application programs and increases the ease of development of new application programs. This paper presents an overview of the interesting aspects of z/Architecture and some of the associated decisions and tradeoffs made in its development. Addressing and other history The z/Architecture [1] continues a succession of architectures for IBM's large computers: the System/360* (1964), System/370* (1970), System/370 Extended Architecture (370-XA, 1983), Enterprise Systems Architecture/370* (ESA/370, 1988), and Enterprise Systems Architecture/390* (ESA/390, 1990) [2] ISAs. The principal evolutionary trait of the processor-related advances in this series has been an increase in both the storage usable by an individual application program and the main storage that can be attached to a model and shared by many programs being executed concurrently. The z/Architecture increases the 31-bit virtual and real (for main storage) address sizes of 370-XA, ESA/370, and ESA/390 to 64 bits, a size large enough to address approximately 1.8 ϫ 10 19 bytes (16 exabytes) of either a single virtual address space or the total main storage of the machine. This is 1.1 ϫ 10 12 times as much storage as is supported by ESA/390! In System/360 through ESA/390, addressing proceeded from 24 bits to 31 bits for all addresses, with transitional support for 26-bit addressing of main storage. The dualaddress-space facility initiated in System/370 and the access registers initiated in ESA/370 increased addressing horizontally by allowing multiple address spaces to be addressed concurrently. The architectures leading to ESA/370 are discussed in References [3-6], and ESA/370 is discussed in Reference [7].

Coupling I/O channels for the IBM eServer z900: Reengineering required

“…to use expanded memory, thus providing more physical memory access through a separated address space. With the z900 64-bit architecture [12], the CF no longer has to use expanded memory. Zone relocation gives each image its own view of a contiguous physical memory address space, or zone, starting at address zero.…”

Design and microarchitecture of the IBM System z10 microprocessor

“…For example, an out-of-order execution pipeline would give a good performance gain, but not enough to make a two times performance improvement. Besides, such a design would require a significant microarchitecture overhaul and an increase in logic content to support the inherently rich and complex IBM z/Architecture * [5]. Also investigated was the possibility of three on-chip simultaneous multithreaded cores with each supporting two threads.…”

The IBM eServer z990 microprocessor

“…Prior CMOS IBM mainframe processors [1][2][3][4] had a relatively simple microarchitecture and were optimized for traditional applications that ran on them. These applications tended to fully exploit the complex instructions in the z/Architecture* instruction set [5,6]; a significant number were written in assembly language (or at least used it for performance-critical routines); and they stressed the storage subsystem. Therefore, the instruction pipeline in these earlier CMOS processors was not superscalar; that is, they could execute only one instruction per clock cycle.…”