Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)
DOI: 10.1109/asic.2000.880700
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Development and application of a macro model for flash EEPROM design

Abstract: Abstrucr-The inclusion of embedded Flash memory in systemson-chip designs enables the addition of many new features. However to enable designers to embed Flash memory in an efficient and competent manner, they must have the capability to simulate full circuit operation. Therefore a flexible Flash EEPROM model is required.An accurate and numerically efficient model for the transient and DC characteristics of Fowler Nordheim (FN) based Flash EEPROM cells has been developed. The model has been extensively validat… Show more

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Cited by 5 publications
(2 citation statements)
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“…The so-called durability means that it can maintain the rated opening window erasing times. At the same time, the process is simple and the transistor area is small, which is the mainstream of current applications [8].…”
Section: Eeprom Cell Typesmentioning
confidence: 99%
“…The so-called durability means that it can maintain the rated opening window erasing times. At the same time, the process is simple and the transistor area is small, which is the mainstream of current applications [8].…”
Section: Eeprom Cell Typesmentioning
confidence: 99%
“…These two device features make this cell attractive to system designers wishing to embed low power NVM in their designs at minimal costs. The development of an accurate model for flash memory is made more difficult by the complicated nature of the cell [4]. In standard flash memory [5], the threshold voltage and, therefore, the drain current of the cell varies as the cell is programmed or erased.…”
Section: Introductionmentioning
confidence: 99%