Developing the WTL3170/3171 Sparc floating-point coprocessors

In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing.There are two main aspects to the application of formal methods in a design process: the formal framework used to specify desired properties of a design and the verification techniques and tools used to reason about the relationship between a specification and a corresponding implementation. We survey a variety of frameworks and techniques proposed in the literature and applied to actual designs. The specification frameworks we describe include temporal logics, predicate logic, abstraction and refinement, as well as containment between -regular languages. The verification techniques presented include model checking, automatatheoretic techniques, automated theorem proving, and approaches that integrate the above methods.In order to provide insight into the scope and limitations of currently available techniques, we present a selection of case studies where formal methods were applied to industrial-scale designs, such as microprocessors, floating-point hardware, protocols, memory subsystems, and communications hardware.

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“…6 The paper does not specify exactly which model. 7 The architecture of this unit has been documented in the literature [Birman et al 1990]. …”

Section: 22mentioning

confidence: 99%

Formal verification in hardware design

Kern

Greenstreet

1999

ACM Trans. Des. Autom. Electron. Syst.

209

117

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“…Several SRT implementations have been reported, including radix 2 dividers by Knowles [11], Kuninobu [12], Vandemeulebroecke [22], and Zuras [23], radix 4 by Birman [3] and Fandrianto [8], radix 8 by Fandrianto [9] and Prabhu [16], and radix 16 by Carter [5] and Taylor [21]. SRT dividers with simplified quotient-digit selection using operand range restriction have been presented in Ercegovac [6], Montuschi [14], and Srinivas [18].…”

Section: Introductionmentioning

confidence: 99%

Minimizing the complexity of SRT tables

Oberman

Flynn

1998

IEEE Trans. VLSI Syst.

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This paper presents an analysis of the complexity of quotient-digit selection tables in SRT division implementations. SRT dividers are widely used in VLSI systems to compute floating-point quotients. These dividers use a fixed number of partial remainder and divisor bits to consult a table to select the next quotient-digit in each iteration. This analysis derives the allowable divisor and partial remainder truncations for radix 2 through radix 32, and it quantifies the relationship between table parameters and the complexity of the tables. Several techniques are presented for further minimizing table complexity. By mapping the tables to a library of standard-cells, delay and area values were measured and are presented for table configurations through radix 32. Several conclusions are drawn based on this data which impacts optimized SRT divider designs.

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“…The classical radix-2 SRT-Redundant method [2] [4] [9] [10] [13] [16] is based on the recursive relationship…”

Section: Srt-redundant Methodsmentioning

confidence: 99%