Developer-soluble gap fill materials for patterning metal trenches in via-first dual-damascene process

Bhave, Mandar; Edwards, Kevin; Washburn, Carlton; Takei, Satoshi; Sakaida, Yasushi; Nakajima, Yasuyuki

doi:10.1117/12.534338

Cited by 13 publications

(2 citation statements)

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“…Also developer-soluble gap fill materials have become available. These materials can be coated thick enough to planarize all the topography and is then recessed to the metal level using a standard development step in the track ( Figure 4) [10,11]. Trench first applications typically result in less deep topography, but the area to fill can be very large (maximum trench size).…”

Section: Materials Related Challenges and Optionsmentioning

confidence: 99%

Lithography options and challenges for sub-45nm node interconnect layers

Maenhoudt

2008

2008 International Interconnect Technology Conference

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Section: Materials Related Challenges and Optionsmentioning

confidence: 99%

Lithography options and challenges for sub-45nm node interconnect layers

Maenhoudt

2008

2008 International Interconnect Technology Conference

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“…In order to promote the development of LSI having higher performance, planarization techniques become indispensable for wider depth-of focus margin in double patterning and Dual Damascene process as shown in Fig.1 [1][2][3][4][5][6][7][8] . Spin coat and etch back process using a conventional organic bottom anti-reflective coating (BARC) or thermal cross-link gap fill material, and then chemical mechanical polishing (CMP) technology as the most suitable processes were reported to decrease the thicknesses bias between the blanket areas and interconnect areas, and between the blanket areas and via arrays.…”

Section: Introductionmentioning

confidence: 99%

Advanced ultraviolet cross-link process and materials for global planarization

Takei

Horiguchi

Ohashi

et al. 2008

Advances in Resist Materials and Processing Technology XXV

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The use of a conventional thermal cross-link materials such as negative resists, anti-reflective coating (BARC), and planarizing layers does not lead to excellent planarization for multilevel interconnects, and specially via arrays prior to trench patterning for an advance lithography.The large thicknesses bias between the blanket areas and interconnect areas, and between the blanket areas and via arrays are usually observed. This large thickness bias creates problems during next lithography by narrowing the process latitude.Recently, chemical mechanical polishing (CMP) technology has been proposed to achieve global planarization. However, the CMP planarization technique is very sensitive to pattern density, and chemical etching reaction had high possibility to increase the dielectric constant.The current CMP technique still requires a new investment in the CMP equipment.In this paper, we reported another novel approach for global planarization using UV cross-link material (XUV TM ) and the dielectric ultra violet exposure unit in coater equipment (TOKYO ELECTRON LTD CLEAN TRACK TM ). This planar technique provides benefits for reducing the thickness bias observed in the 22-65 nm generation lithography and imprint processes. Using this technique, a remarkable reduction in via topography with 1.1 µm as a depth and 0.9-1.0 µm as a diameter has been achieved excellent thickness bias less than 20 nm.And, the planarization of the film obtained from the XUV TM was very high as compared with that of the film obtained from thermal cross-link gap fill material as the reference, particularly under severe coating conditions such as dense patterns.

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