Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

Nose, Keisuke; Shibayama, A.; Kodama, Hiroshi; Mizuno, Masayuki; Edahiro, Masato; Nishi, N.

doi:10.1109/isscc.2005.1493986

Cited by 15 publications

(5 citation statements)

References 2 publications

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“…The latency (L k ) for processing the request originating on the k th transmit clock edge is defined as the time between that Proceedings of the 19th International Conference on VLSI Design (VLSID'06) edge and the corresponding enabled receive edge receiving the request. L k = t( rx_en k ) -t( tx k ) (4) where t( tx k ) is the time to the k th transmit clock edge from the CS heartbeat edge, t( rx_en k ) is the time to the corresponding enabled receive edge from the CS heartbeat edge and k indexes all the transmit clock edges in a CS period (Fig. 8).…”

Section: Resultsmentioning

confidence: 99%

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Deterministic low-latency data transfer across non-integral ratio clock domains

Balasubramanian

Natarajan

Franza

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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System on a chip (SOC) implementations typically require their functional blocks to run at different clock frequencies in order to better optimize the system performance for a wide variety of applications while staying within the power envelope. The functional blocks are required to exchange data between themselves and with off-chip memory through a shared system interface module. Data transfers across this interface need to occur at low latency and high bandwidth to achieve the targeted chip performance. Also data transfers need to be deterministic to ease post-silicon debug and satisfy lock-step customers. This precludes the use of synchronizers. Fractional Clock Data Transfer (FCDT) is a solution that ensures full determinism while achieving very low latencies. This paper describes the FCDT scheme in general and proposes a sample implementation .

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Section: Resultsmentioning

confidence: 99%

“…A data transfer scheme in the context of a periodic all-in-phase clock system is proposed in [4]. The clock generation scheme ensures that all on-chip clocks are aligned to a common reference clock (REFCLK) edge.…”

Section: Introductionmentioning

confidence: 99%

Deterministic low-latency data transfer across non-integral ratio clock domains

Balasubramanian

Natarajan

Franza

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

View full text Add to dashboard Cite

show abstract

“…Usually pre-divider value (R), multiplier value (N) and post-divider value (P) are programmable, enabling us to synthesize the frequency required for a particular IP core from the crystal oscillator frequency [12,13]. This conventional approach needs 'n' number of PLLs to generate the 'n' unique frequencies required for the cores in a SoC [14,15]. In trivial cases, where the frequencies of two or more cores are multiples of each other, the highest frequency can be generated with a PLL and others can be derived from it by clock dividers.…”

Section: Clock Generation In Present Day Soc: Methodology and Issuesmentioning

confidence: 99%

A novel clock generation algorithm for system-on-chip based on least common multiple

Reuben

Kittur

Shoaib

2014

Computers & Electrical Engineering

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“…For a wide-range DLL, the minimum of 2 is not allowed and of 6 is chosen in this case. By neglecting the delays contributed by the PD, the SAR controller and so on, for a wide-range DLL is expressed as (2) where represents the delay for the delay line controlled with the code which is half the full scale and indicates the minimum input clock period in a wide-range operation. Assume the total number of bits is and the ratio between the maximum and the minimum operating frequencies is .…”

Section: The Proposed Vsar Algorithm and The All-digital Dllmentioning

confidence: 99%

“…Thus, the harmonic locking is no longer an issue. According to (2), in the VSAR controller is the minimum of 2. The lock time for the DLL with the VSAR controller is given as (4) where is the number of bits required for correct lock.…”

Section: The Proposed Vsar Algorithm and The All-digital Dllmentioning

confidence: 99%

A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

Yang

Liu

2007

IEEE J. Solid-State Circuits

135

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A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18 m CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40 MHz to 550 MHz without the harmonic-locking issue. It dissipates 12.6 mW from a 1.8 V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550 MHz are 1.5 ps and 12 ps, respectively.

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Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

Cited by 15 publications

References 2 publications

Deterministic low-latency data transfer across non-integral ratio clock domains

Deterministic low-latency data transfer across non-integral ratio clock domains

A novel clock generation algorithm for system-on-chip based on least common multiple

A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

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